Lines Matching refs:XTENSA_PMU_MASK
50 #define XTENSA_PMU_MASK(select, mask) \ macro
68 [PERF_COUNT_HW_CPU_CYCLES] = XTENSA_PMU_MASK(0, 0x1),
69 [PERF_COUNT_HW_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0xffff),
70 [PERF_COUNT_HW_CACHE_REFERENCES] = XTENSA_PMU_MASK(10, 0x1),
71 [PERF_COUNT_HW_CACHE_MISSES] = XTENSA_PMU_MASK(12, 0x1),
73 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XTENSA_PMU_MASK(2, 0x490),
75 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XTENSA_PMU_MASK(4, 0x1ff),
77 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = XTENSA_PMU_MASK(3, 0x1ff),
85 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(10, 0x1),
86 [C(RESULT_MISS)] = XTENSA_PMU_MASK(10, 0x2),
89 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(11, 0x1),
90 [C(RESULT_MISS)] = XTENSA_PMU_MASK(11, 0x2),
95 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(8, 0x1),
96 [C(RESULT_MISS)] = XTENSA_PMU_MASK(8, 0x2),
101 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(9, 0x1),
102 [C(RESULT_MISS)] = XTENSA_PMU_MASK(9, 0x8),
107 [C(RESULT_ACCESS)] = XTENSA_PMU_MASK(7, 0x1),
108 [C(RESULT_MISS)] = XTENSA_PMU_MASK(7, 0x8),