Lines Matching +full:0 +full:xb0000000

23 #define XCHAL_PAGE_TABLE_VADDR	__XTENSA_UL_CONST(0x80000000)
24 #define XCHAL_PAGE_TABLE_SIZE	__XTENSA_UL_CONST(0x00400000)
28 #define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xd0000000)
29 #define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xd8000000)
30 #define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x08000000)
31 #define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x08000000)
37 #define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xb0000000)
38 #define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xc0000000)
39 #define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x10000000)
40 #define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x10000000)
46 #define XCHAL_KSEG_CACHED_VADDR	__XTENSA_UL_CONST(0xa0000000)
47 #define XCHAL_KSEG_BYPASS_VADDR	__XTENSA_UL_CONST(0xc0000000)
48 #define XCHAL_KSEG_SIZE		__XTENSA_UL_CONST(0x20000000)
49 #define XCHAL_KSEG_ALIGNMENT	__XTENSA_UL_CONST(0x10000000)
60 #define XCHAL_KSEG_PADDR	__XTENSA_UL_CONST(0x00000000)
72 #define XCHAL_KIO_CACHED_VADDR		0xe0000000
73 #define XCHAL_KIO_BYPASS_VADDR		0xf0000000
74 #define XCHAL_KIO_DEFAULT_PADDR		0xf0000000
77 #define XCHAL_KIO_DEFAULT_PADDR		0x90000000
79 #define XCHAL_KIO_SIZE			0x10000000