Lines Matching +full:lcd +full:- +full:wb
1 # SPDX-License-Identifier: GPL-2.0
61 Xtensa processors are 32-bit RISC machines designed by Tensilica
66 a home page at <http://www.linux-xtensa.org/>.
105 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1)
111 …def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null…
120 bool "fsf - default (not generic) configuration"
124 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
131 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
167 ie: it supports a TLB with auto-loading, page protection.
224 byte and 2-byte access to memory attached to instruction bus.
231 This option is used to indicate that the system-on-a-chip (SOC)
245 bool "Enable Symmetric multi-processing support"
254 int "Maximum number of CPUs (2-32)"
413 XT2000 is the name of Tensilica's feature-rich emulation platform.
454 architectures, you should supply some command-line options at build
501 tristate "Host file-based simulated block device support"
510 int "Number of host file-based simulated block devices"
533 Another simulated disk in a host file for a buildroot-independent
537 bool "Enable XTFPGA LCD driver"
541 There's a 2x16 LCD on most of XTFPGA boards, kernel may output
548 hex "XTFPGA LCD base address"
552 Base address of the LCD controller inside KIO region.
553 Different boards from XTFPGA family have LCD controller at different
558 bool "Use 8-bit access to XTFPGA LCD"
562 LCD may be connected with 4- or 8-bit interface, 8-bit access may
563 only be used with 8-bit interface. Please consult prototyping user
579 This unfortunately won't work for U-Boot and likely also won't
585 xt-gdb can't place a Software Breakpoint in the 0XD region prior
593 Selecting this will cause U-Boot to set the KERNEL Load and Entry
599 bool "Kernel Execute-In-Place from ROM"
602 Execute-In-Place allows the kernel to run from non-volatile storage
605 to RAM. Read-write sections, such as the data section and stack,
626 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
627 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
633 4: WB cached,
640 1: WB cache,
645 1: WB cache,
646 2: WB, no-write-allocate cache,
692 placed at their hardware-defined locations.
709 XIP-aware MTD support.