Lines Matching +full:0 +full:xc01
25 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
26 #define PIRQ_VERSION 0x0100
28 #define IRT_SIGNATURE (('$' << 0) + ('I' << 8) + ('R' << 16) + ('T' << 24))
39 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
43 unsigned int pcibios_irq_mask = 0xfff8;
46 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
47 0, 0, 0, 0, 1000, 100000, 100000, 100000
87 sum = 0; in pirq_check_routing_table()
88 for (i = 0; i < rt->size; i++) in pirq_check_routing_table()
91 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%lx\n", in pirq_check_routing_table()
143 DBG(KERN_DEBUG "PCI: $IRT Interrupt Routing Table found at 0x%lx\n", in pirq_convert_irt_table()
155 for (i = 0; i < ir->used; i++) in pirq_convert_irt_table()
159 sum = 0; in pirq_convert_irt_table()
160 for (i = 0; i < size; i++) in pirq_convert_irt_table()
168 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
173 u8 * const bios_start = (u8 *)__va(0xf0000); in pirq_find_routing_table()
174 u8 * const bios_end = (u8 *)__va(0x100000); in pirq_find_routing_table()
215 memset(busmap, 0, sizeof(busmap)); in pirq_peer_trick()
216 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { in pirq_peer_trick()
223 for (j = 0; j < 4; j++) in pirq_peer_trick()
231 if (!busmap[i] || pci_find_bus(0, i)) in pirq_peer_trick()
240 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
271 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2
294 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O
295 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines
303 * by writing the value of 0xc5 to the Lock Register at index 0x03
306 * Lock Register being written with 0xc5 again.
314 #define PC_CONF_FINALI_LOCK 0x03u
315 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u
316 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u
317 #define PC_CONF_FINALI_PCI_INTX_SENS 0x44u
319 #define PC_CONF_FINALI_LOCK_KEY 0xc5u
327 return index & 1 ? x >> 4 : x & 0xf; in read_pc_conf_nybble()
336 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val; in write_pc_conf_nybble()
343 * - bit 0 selects between INTx Routing Table Mapping Registers,
347 * - bits 7:4 map to bits 3:0 of the PCI INTx Sensitivity Register.
353 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 in pirq_finali_get()
363 pc_conf_set(PC_CONF_FINALI_LOCK, 0); in pirq_finali_get()
372 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 in pirq_finali_set()
379 return 0; in pirq_finali_set()
385 pc_conf_set(PC_CONF_FINALI_LOCK, 0); in pirq_finali_set()
393 u8 mask = ~((pirq & 0xf0u) >> 4); in pirq_finali_lvl()
403 pc_conf_set(PC_CONF_FINALI_LOCK, 0); in pirq_finali_lvl()
418 return (nr & 1) ? (x >> 4) : (x & 0xf); in read_config_nybble()
428 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); in write_config_nybble()
439 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; in pirq_ali_get()
442 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; in pirq_ali_get()
447 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; in pirq_ali_set()
452 write_config_nybble(router, 0x48, pirq-1, val); in pirq_ali_set()
455 return 0; in pirq_ali_set()
466 * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the
471 * by writing the value of 0x0f to the ESC ID Register at index 0x02
474 * ESC ID Register being written with 0x0f again.
485 #define PC_CONF_I82374_ESC_ID 0x02u
486 #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u
488 #define PC_CONF_I82374_ESC_ID_KEY 0x0fu
503 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); in pirq_esc_get()
505 return (x < 16) ? x : 0; in pirq_esc_get()
521 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); in pirq_esc_set()
535 return (x < 16) ? x : 0; in pirq_piix_get()
549 * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67
560 #define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u
572 return (x < 16) ? x : 0; in pirq_ib_get()
595 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); in pirq_via_get()
600 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); in pirq_via_set()
614 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); in pirq_via586_get()
622 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); in pirq_via586_set()
628 * FIXME: pirqmap may be { 1, 0, 3, 2 },
633 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; in pirq_ite_get()
636 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); in pirq_ite_get()
641 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; in pirq_ite_set()
644 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); in pirq_ite_set()
654 return read_config_nybble(router, 0xb8, pirq >> 4); in pirq_opti_get()
659 write_config_nybble(router, 0xb8, pirq >> 4, irq); in pirq_opti_set()
664 * Cyrix: nibble offset 0x5C
665 * 0x5C bits 7:4 is INTB bits 3:0 is INTA
666 * 0x5D bits 7:4 is INTD bits 3:0 is INTC
670 return read_config_nybble(router, 0x5C, (pirq-1)^1); in pirq_cyrix_get()
675 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); in pirq_cyrix_set()
688 * host bridge, at 0xc0/0xc1/0xc2/0xc3 respectively for the PCI INT
690 * 3:0 select the 8259A IRQ line as follows:
718 #define PCI_SIS497_INTA_TO_IRQ_LINK 0xc0u
720 #define PIRQ_SIS497_IRQ_MASK 0x0fu
721 #define PIRQ_SIS497_IRQ_ENABLE 0x80u
734 return (x & PIRQ_SIS497_IRQ_ENABLE) ? (x & PIRQ_SIS497_IRQ_MASK) : 0; in pirq_sis497_get()
765 * bit 7 IRQ mapping enabled (0) or disabled (1)
767 * bits [3:0] IRQ to map to
769 * reserved: 0, 1, 2, 8, 13
771 * The config-space registers located at 0x41/0x42/0x43/0x44 are
774 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
780 * router (ISA-bridge) should be 0x01 or 0xb0.
782 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
788 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
790 * 0x61: IDEIRQ:
792 * bit 4 channel-select primary (0), secondary (1)
794 * 0x62: USBIRQ:
795 * bit 6 OHCI function disabled (0), enabled (1)
797 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
799 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
806 * router revision 0x04 and there are changes in the register layout
809 * Onchip routing for router rev-id 0x04 (try-and-error observation)
811 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
815 #define PIRQ_SIS503_IRQ_MASK 0x0f
816 #define PIRQ_SIS503_IRQ_DISABLE 0x80
817 #define PIRQ_SIS503_USB_ENABLE 0x40
826 if (reg >= 0x01 && reg <= 0x04) in pirq_sis503_get()
827 reg += 0x40; in pirq_sis503_get()
829 return (x & PIRQ_SIS503_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS503_IRQ_MASK); in pirq_sis503_get()
839 if (reg >= 0x01 && reg <= 0x04) in pirq_sis503_set()
840 reg += 0x40; in pirq_sis503_set()
850 * VLSI: nibble offset 0x74 - educated guess due to routing table and
862 return 0; in pirq_vlsi_get()
864 return read_config_nybble(router, 0x74, pirq-1); in pirq_vlsi_get()
872 return 0; in pirq_vlsi_set()
874 write_config_nybble(router, 0x74, pirq-1, irq); in pirq_vlsi_set()
880 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
881 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
886 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
887 * and 0x03 for SMBus.
891 outb(pirq, 0xc00); in pirq_serverworks_get()
892 return inb(0xc01) & 0xf; in pirq_serverworks_get()
898 outb(pirq, 0xc00); in pirq_serverworks_set()
899 outb(irq, 0xc01); in pirq_serverworks_set()
905 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
906 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
908 * offset 0x56 0-3 PIRQA 4-7 PIRQB
909 * offset 0x57 0-3 PIRQC 4-7 PIRQD
914 irq = 0; in pirq_amd756_get()
916 irq = read_config_nybble(router, 0x56, pirq - 1); in pirq_amd756_get()
929 write_config_nybble(router, 0x56, pirq - 1, irq); in pirq_amd756_set()
938 outb(0x10 + ((pirq - 1) >> 1), 0x24); in pirq_pico_get()
939 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); in pirq_pico_get()
946 outb(0x10 + ((pirq - 1) >> 1), 0x24); in pirq_pico_set()
947 x = inb(0x26); in pirq_pico_set()
948 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); in pirq_pico_set()
949 outb(x, 0x26); in pirq_pico_set()
974 return 0; in intel_router_probe()
1048 return 0; in intel_router_probe()
1103 return 0; in via_router_probe()
1115 return 0; in vlsi_router_probe()
1130 return 0; in serverworks_router_probe()
1147 return 0; in sis_router_probe()
1159 return 0; in cyrix_router_probe()
1171 return 0; in opti_router_probe()
1183 return 0; in ite_router_probe()
1202 return 0; in ali_router_probe()
1218 return 0; in amd_router_probe()
1240 return 0; in pico_router_probe()
1256 { 0, NULL }
1313 dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus, in pirq_find_router()
1399 int irq = 0; in pcibios_lookup_irq()
1409 return 0; in pcibios_lookup_irq()
1413 return 0; in pcibios_lookup_irq()
1418 return 0; in pcibios_lookup_irq()
1425 return 0; in pcibios_lookup_irq()
1431 return 0; in pcibios_lookup_irq()
1440 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { in pcibios_lookup_irq()
1449 pirq = 0x68; in pcibios_lookup_irq()
1450 mask = 0x400; in pcibios_lookup_irq()
1462 newirq = 0; in pcibios_lookup_irq()
1468 for (i = 0; i < 16; i++) { in pcibios_lookup_irq()
1479 if ((pirq & 0xf0) == 0xf0) { in pcibios_lookup_irq()
1480 irq = pirq & 0xf; in pcibios_lookup_irq()
1507 return 0; in pcibios_lookup_irq()
1562 dev->irq = 0; in pcibios_fixup_irqs()
1570 pirq_penalty[dev->irq] = 0; in pcibios_fixup_irqs()
1587 pcibios_lookup_irq(dev, 0); in pcibios_fixup_irqs()
1602 return 0; in fix_broken_hp_bios_irq9()
1616 return 0; in fix_acer_tm360_irqrouting()
1666 for (i = 0; i < 16; i++) in pcibios_irq_init()
1721 u8 pin = 0; in pirq_enable_irq()
1728 return 0; in pirq_enable_irq()
1735 if (dev->irq_managed && dev->irq > 0) in pirq_enable_irq()
1736 return 0; in pirq_enable_irq()
1747 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ in pirq_enable_irq()
1754 if (irq >= 0) in pirq_enable_irq()
1762 if (irq >= 0) { in pirq_enable_irq()
1767 return 0; in pirq_enable_irq()
1781 !(dev->class & 0x5)) in pirq_enable_irq()
1782 return 0; in pirq_enable_irq()
1787 return 0; in pirq_enable_irq()
1807 dev->irq = 0; in pirq_disable_irq()
1808 dev->irq_managed = 0; in pirq_disable_irq()