1 // SPDX-License-Identifier: GPL-2.0
8  *   - configuration space is memory mapped (as defined by MCFG)
9  *   - Lincroft devices also have a real, type 1 configuration space
10  *   - Early Lincroft silicon has a type 1 access bug that will cause
11  *     a hang if non-existent devices are accessed
12  *   - some devices have the "fixed BAR" capability, which means
36 #include <asm/intel-family.h>
37 #include <asm/intel-mid.h>
46 /* Fixed BAR fields */
47 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00	/* Fixed BAR (TBD) */
58  * fixed_bar_cap - return the offset of the fixed BAR cap if found
62  * Look for the fixed BAR cap on @bus and @devfn, returning its offset
76 		if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,  in fixed_bar_cap()
85 			raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,  in fixed_bar_cap()
100 	u32 size;  in pci_device_update_fixed()  local
102 	int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;  in pci_device_update_fixed()
105 	busnum = bus->number;  in pci_device_update_fixed()
110 		raw_pci_ext_ops->read(domain, busnum, devfn,  in pci_device_update_fixed()
111 			       offset + 8 + (bar * 4), 4, &size);  in pci_device_update_fixed()
113 		/* Turn the size into a decode pattern for the sizing code */  in pci_device_update_fixed()
114 		if (size) {  in pci_device_update_fixed()
115 			decode = size - 1;  in pci_device_update_fixed()
122 			decode = ~(decode - 1);  in pci_device_update_fixed()
128 		 * If val is all ones, the core code is trying to size the reg,  in pci_device_update_fixed()
129 		 * so update the mmconfig space with the real size.  in pci_device_update_fixed()
131 		 * Note: this assumes the fixed size we got is a power of two.  in pci_device_update_fixed()
133 		return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,  in pci_device_update_fixed()
138 	return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);  in pci_device_update_fixed()
142  * type1_access_ok - check whether to use type 1
172 		    int size, u32 *value)  in pci_read()  argument
174 	if (type1_access_ok(bus->number, devfn, where))  in pci_read()
175 		return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,  in pci_read()
176 					devfn, where, size, value);  in pci_read()
177 	return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,  in pci_read()
178 			      devfn, where, size, value);  in pci_read()
182 		     int size, u32 value)  in pci_write()  argument
194 	 * Devices with fixed BARs need special handling:  in pci_write()
195 	 *   - BAR sizing code will save, write ~0, read size, restore  in pci_write()
196 	 *   - so writes to fixed BARs need special handling  in pci_write()
197 	 *   - other writes to fixed BAR devices should go through mmconfig  in pci_write()
202 		return pci_device_update_fixed(bus, devfn, where, size, value,  in pci_write()
209 	 *       non-existent devices, so just eat the write in that case.  in pci_write()
211 	if (type1_access_ok(bus->number, devfn, where))  in pci_write()
212 		return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,  in pci_write()
213 					      devfn, where, size, value);  in pci_write()
214 	return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,  in pci_write()
215 			       where, size, value);  in pci_write()
232 	if (dev->irq_managed && dev->irq > 0)  in intel_mid_pci_irq_enable()
237 		dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret);  in intel_mid_pci_irq_enable()
243 		model = id->model;  in intel_mid_pci_irq_enable()
255 			if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)  in intel_mid_pci_irq_enable()
256 				return -EBUSY;  in intel_mid_pci_irq_enable()
264 			if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)  in intel_mid_pci_irq_enable()
273 	ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low);  in intel_mid_pci_irq_enable()
283 	dev->irq = ret;  in intel_mid_pci_irq_enable()
284 	dev->irq_managed = 1;  in intel_mid_pci_irq_enable()
291 	if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&  in intel_mid_pci_irq_disable()
292 	    dev->irq > 0) {  in intel_mid_pci_irq_disable()
293 		mp_unmap_irq(dev->irq);  in intel_mid_pci_irq_disable()
294 		dev->irq_managed = 0;  in intel_mid_pci_irq_disable()
304  * intel_mid_pci_init - installs intel_mid_pci_ops
330 	 * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.  in pci_d3delay_fixup()
338 	if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))  in pci_d3delay_fixup()
340 	dev->d3hot_delay = 0;  in pci_d3delay_fixup()
352 	pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);  in mid_power_off_one_device()
353 	dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);  in mid_power_off_one_device()
371 	 * arch/x86/platform/intel-mid/pwr.c.  in mid_power_off_devices()
379  * Langwell devices reside at fixed offsets, don't try to move them.
384 	u32 size;  in pci_fixed_bar_fixup()  local
391 	if (dev->cfg_size < PCIE_CAP_OFFSET + 4)  in pci_fixed_bar_fixup()
394 	/* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */  in pci_fixed_bar_fixup()
395 	offset = fixed_bar_cap(dev->bus, dev->devfn);  in pci_fixed_bar_fixup()
396 	if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||  in pci_fixed_bar_fixup()
397 	    PCI_DEVFN(2, 2) == dev->devfn)  in pci_fixed_bar_fixup()
401 		pci_read_config_dword(dev, offset + 8 + (i * 4), &size);  in pci_fixed_bar_fixup()
402 		dev->resource[i].end = dev->resource[i].start + size - 1;  in pci_fixed_bar_fixup()
403 		dev->resource[i].flags |= IORESOURCE_PCI_FIXED;  in pci_fixed_bar_fixup()