31  * CMCI can be delivered to multiple cpus that share a machine check bank
32  * so we need to designate a single cpu to process errors logged in each bank
61  * MCi_CTL2 threshold for each bank when there is no storm.
62  * Default value for each bank may have been set by BIOS.
71  * bank because both corrected and uncorrected errors may be logged
72  * in the same bank and signalled with CMCI. The threshold only applies
137 static void cmci_set_threshold(int bank, int thresh)  in cmci_set_threshold()  argument
143 	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);  in cmci_set_threshold()
145 	wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh);  in cmci_set_threshold()
149 void mce_intel_handle_storm(int bank, bool on)  in mce_intel_handle_storm()  argument
152 		cmci_set_threshold(bank, CMCI_STORM_THRESHOLD);  in mce_intel_handle_storm()
154 		cmci_set_threshold(bank, cmci_threshold[bank]);  in mce_intel_handle_storm()
170  * ownership of a bank.
171  * 1: CPU already owns this bank
172  * 2: BIOS owns this bank
173  * 3: Some other CPU owns this bank
175 static bool cmci_skip_bank(int bank, u64 *val)  in cmci_skip_bank()  argument
179 	if (test_bit(bank, owned))  in cmci_skip_bank()
183 	if (test_bit(bank, mce_banks_ce_disabled))  in cmci_skip_bank()
186 	rdmsrl(MSR_IA32_MCx_CTL2(bank), *val);  in cmci_skip_bank()
190 		clear_bit(bank, owned);  in cmci_skip_bank()
191 		__clear_bit(bank, this_cpu_ptr(mce_poll_banks));  in cmci_skip_bank()
200  * 1: If this bank is in storm mode from whichever CPU was
227  * Try to claim ownership of a bank.
229 static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_wrong_thresh)  in cmci_claim_bank()  argument
234 	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);  in cmci_claim_bank()
235 	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);  in cmci_claim_bank()
237 	/* If the enable bit did not stick, this bank should be polled. */  in cmci_claim_bank()
239 		WARN_ON(!test_bit(bank, this_cpu_ptr(mce_poll_banks)));  in cmci_claim_bank()
240 		storm->banks[bank].poll_only = true;  in cmci_claim_bank()
245 	set_bit(bank, (void *)this_cpu_ptr(&mce_banks_owned));  in cmci_claim_bank()
248 		pr_notice("CPU%d BANK%d CMCI inherited storm\n", smp_processor_id(), bank);  in cmci_claim_bank()
249 		mce_inherit_storm(bank);  in cmci_claim_bank()
250 		cmci_storm_begin(bank);  in cmci_claim_bank()
252 		__clear_bit(bank, this_cpu_ptr(mce_poll_banks));  in cmci_claim_bank()
265 	/* Save default threshold for each bank */  in cmci_claim_bank()
266 	if (cmci_threshold[bank] == 0)  in cmci_claim_bank()
267 		cmci_threshold[bank] = val & MCI_CTL2_CMCI_THRESHOLD_MASK;  in cmci_claim_bank()
320 static void __cmci_disable_bank(int bank)  in __cmci_disable_bank()  argument
324 	if (!test_bit(bank, this_cpu_ptr(mce_banks_owned)))  in __cmci_disable_bank()
326 	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);  in __cmci_disable_bank()
328 	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);  in __cmci_disable_bank()
329 	__clear_bit(bank, this_cpu_ptr(mce_banks_owned));  in __cmci_disable_bank()
332 		cmci_storm_end(bank);  in __cmci_disable_bank()
383 void cmci_disable_bank(int bank)  in cmci_disable_bank()  argument
392 	__cmci_disable_bank(bank);  in cmci_disable_bank()
396 /* Bank polling function when CMCI is disabled. */
492 	    (m->bank == 0) &&  in intel_filter_mce()