1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
60  * With a name like MSR_TEST_CTL it should go without saying, but don't touch
67  * Processors which have self-snooping capability can handle conflicting
75 	switch (c->x86_vfm) {  in check_memory_type_self_snoop_errata()
107 	if (c->x86 != 6)  in probe_xeon_phi_r3mwait()
109 	switch (c->x86_vfm) {  in probe_xeon_phi_r3mwait()
131  * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132  * - https://kb.vmware.com/s/article/52345
133  * - Microcode revisions observed in the wild
134  * - Release note from 20180108 microcode release
177 		if (c->x86_vfm == spectre_bad_microcodes[i].vfm &&  in bad_spectre_microcode()
178 		    c->x86_stepping == spectre_bad_microcodes[i].stepping)  in bad_spectre_microcode()
179 			return (c->microcode <= spectre_bad_microcodes[i].microcode);  in bad_spectre_microcode()
216 	c->x86_phys_bits -= keyid_bits;  in detect_tme_early()
226 	if (c->x86 < 6 || (c->x86 == 6 && c->x86_model < 0xd))  in intel_unlock_cpuid_leafs()
234 		c->cpuid_level = cpuid_eax(0);  in intel_unlock_cpuid_leafs()
241 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||  in early_init_intel()
242 		(c->x86 == 0x6 && c->x86_model >= 0x0e))  in early_init_intel()
245 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))  in early_init_intel()
246 		c->microcode = intel_get_microcode_revision();  in early_init_intel()
272 	if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 &&  in early_init_intel()
273 	    c->microcode < 0x20e) {  in early_init_intel()
282 	if (c->x86 == 15 && c->x86_cache_alignment == 64)  in early_init_intel()
283 		c->x86_cache_alignment = 128;  in early_init_intel()
287 	if (c->x86 == 0xF && c->x86_model == 0x3  in early_init_intel()
288 	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))  in early_init_intel()
289 		c->x86_phys_bits = 36;  in early_init_intel()
292 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_intel()
293 	 * with P/T states and does not stop in deep C-states.  in early_init_intel()
296 	 * cabinets - we turn it off in that case explicitly.)  in early_init_intel()
298 	if (c->x86_power & (1 << 8)) {  in early_init_intel()
304 	switch (c->x86_vfm) {  in early_init_intel()
324 	if (c->x86_vfm >= INTEL_PENTIUM_PRO &&  in early_init_intel()
325 	    c->x86_vfm <= INTEL_CORE_YONAH)  in early_init_intel()
332 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
351 	if (c->x86_vfm == INTEL_QUARK_X1000) {  in early_init_intel()
394 	if (!c->cpu_index)  in intel_smp_check()
400 	if (c->x86 == 5 &&  in intel_smp_check()
401 	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&  in intel_smp_check()
402 	    c->x86_model <= 3) {  in intel_smp_check()
429 	if (c->x86 == 5 && c->x86_model < 9) {  in intel_workarounds()
434 			pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");  in intel_workarounds()
444 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)  in intel_workarounds()
462 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {  in intel_workarounds()
476 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&  in intel_workarounds()
477 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))  in intel_workarounds()
485 	switch (c->x86) {  in intel_workarounds()
490 	case 6:		/* PII/PIII only like movsl with 8-byte alignment */  in intel_workarounds()
493 	case 15:	/* P4 is OK down to 8-byte alignment */  in intel_workarounds()
563 	if (c->cpuid_level > 9) {  in init_intel()
584 	    (c->x86_vfm == INTEL_CORE2_DUNNINGTON ||  in init_intel()
585 	     c->x86_vfm == INTEL_NEHALEM_EX ||  in init_intel()
586 	     c->x86_vfm == INTEL_WESTMERE_EX))  in init_intel()
589 	if (boot_cpu_has(X86_FEATURE_MWAIT) && c->x86_vfm == INTEL_ATOM_GOLDMONT)  in init_intel()
593 	if (c->x86 == 15)  in init_intel()
594 		c->x86_cache_alignment = c->x86_clflush_size * 2;  in init_intel()
595 	if (c->x86 == 6)  in init_intel()
603 	if (c->x86 == 6) {  in init_intel()
604 		unsigned int l2 = c->x86_cache_size;  in init_intel()
607 		switch (c->x86_model) {  in init_intel()
618 			else if (c->x86_stepping == 0 || c->x86_stepping == 5)  in init_intel()
619 				p = "Celeron-A";  in init_intel()
629 			strcpy(c->x86_model_id, p);  in init_intel()
632 	if (c->x86 == 15)  in init_intel()
634 	if (c->x86 == 6)  in init_intel()
660 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))  in intel_size_cache()
664 	 * Intel Quark SoC X1000 contains a 4-way set associative  in intel_size_cache()
667 	if ((c->x86 == 5) && (c->x86_model == 9))  in intel_size_cache()
695 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
697 	{ 0x03, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way set associative" },
698 	{ 0x04, TLB_DATA_4M,		8,	" TLB_DATA 4 MByte pages, 4-way set associative" },
699 	{ 0x05, TLB_DATA_4M,		32,	" TLB_DATA 4 MByte pages, 4-way set associative" },
700 	{ 0x0b, TLB_INST_4M,		4,	" TLB_INST 4 MByte pages, 4-way set associative" },
702 	{ 0x50, TLB_INST_ALL,		64,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
703 	{ 0x51, TLB_INST_ALL,		128,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
704 	{ 0x52, TLB_INST_ALL,		256,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
705 	{ 0x55, TLB_INST_2M_4M,		7,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
706 	{ 0x56, TLB_DATA0_4M,		16,	" TLB_DATA0 4 MByte pages, 4-way set associative" },
707 	{ 0x57, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, 4-way associative" },
709 	{ 0x5a, TLB_DATA0_2M_4M,	32,	" TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
714 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
715 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
716 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
718 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
719 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
720 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
721 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
722 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
723 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
724 	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },
725 	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },
726 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
727 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
728 	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
729 	{ 0xc2, TLB_DATA_2M_4M,		16,	" TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
730 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
827 	if (c->cpuid_level < 2)  in intel_detect_tlb()
854 			  [0] = "486 DX-25/33",
855 			  [1] = "486 DX-50",
860 			  [7] = "486 DX/2-WB",
862 			  [9] = "486 DX/4-WB"
867 			  [0] = "Pentium 60/66 A-step",
869 			  [2] = "Pentium 75 - 200",
872 			  [7] = "Mobile Pentium 75 - 200",
879 			  [0] = "Pentium Pro A-step",
1077  * If a CPU goes offline with pending delayed work to re-enable split lock
1080  * different CPU probably won't re-enable split lock detection. This is a
1084  * Unconditionally re-enable detection here.
1098 	if (!current->reported_split_lock)  in split_lock_warn()
1100 				    current->comm, current->pid, ip);  in split_lock_warn()
1101 	current->reported_split_lock = 1;  in split_lock_warn()
1114 		if (down_interruptible(&buslock_sem) == -EINTR)  in split_lock_warn()
1137 		     current->comm, current->pid,  in handle_guest_split_lock()
1140 	current->thread.error_code = 0;  in handle_guest_split_lock()
1141 	current->thread.trap_nr = X86_TRAP_AC;  in handle_guest_split_lock()
1173 	if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)  in handle_user_split_lock()
1175 	split_lock_warn(regs->ip);  in handle_user_split_lock()
1192 				    current->comm, current->pid, regs->ip);  in handle_bus_lock()
1201  * CPU models that are known to have the per-core split-lock detection
1256 …	pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");  in sld_state_show()
1261 			pr_info("#DB: warning on user-space bus_locks\n");  in sld_state_show()
1266 …pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_loc…  in sld_state_show()
1268 			pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",  in sld_state_show()
1270 				" from non-WB" : "");  in sld_state_show()
1290  * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU