1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <asm/spec-ctrl.h>
20 #include <asm/pci-direct.h>
71  *	and	section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
97 #define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */  in init_amd_k5()
100 	if (c->x86_model == 9 || c->x86_model == 10) {  in init_amd_k5()
111 	int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);  in init_amd_k6()
113 	if (c->x86_model < 6) {  in init_amd_k6()
114 		/* Based on AMD doc 20734R - June 2000 */  in init_amd_k6()
115 		if (c->x86_model == 0) {  in init_amd_k6()
122 	if (c->x86_model == 6 && c->x86_stepping == 1) {  in init_amd_k6()
128 		pr_info("AMD K6 stepping B detected - ");  in init_amd_k6()
139 		while (n--)  in init_amd_k6()
142 		d = d2-d;  in init_amd_k6()
151 	if (c->x86_model < 8 ||  in init_amd_k6()
152 	   (c->x86_model == 8 && c->x86_stepping < 8)) {  in init_amd_k6()
171 	if ((c->x86_model == 8 && c->x86_stepping > 7) ||  in init_amd_k6()
172 	     c->x86_model == 9 || c->x86_model == 13) {  in init_amd_k6()
193 	if (c->x86_model == 10) {  in init_amd_k6()
211 	if (c->x86_model >= 6 && c->x86_model <= 10) {  in init_amd_k7()
224 	if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {  in init_amd_k7()
234 	if (!c->cpu_index)  in init_amd_k7()
242 	if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||  in init_amd_k7()
243 	    (c->x86_stepping == 1)))  in init_amd_k7()
247 	if ((c->x86_model == 7) && (c->x86_stepping == 0))  in init_amd_k7()
254 	 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for  in init_amd_k7()
257 	if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||  in init_amd_k7()
258 	    ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||  in init_amd_k7()
259 	     (c->x86_model > 7))  in init_amd_k7()
266 	 * Don't taint if we are running SMP kernel on a single non-MP  in init_amd_k7()
284 	for (i = apicid - 1; i >= 0; i--) {  in nearby_node()
303 	unsigned apicid = c->topo.apicid;  in srat_detect_node()
310 	 * On multi-fabric platform (e.g. Numascale NumaChip) a  in srat_detect_node()
311 	 * platform-specific handler needs to be called to fixup some  in srat_detect_node()
321 		 * - The CPU is missing memory and no node was created.  In  in srat_detect_node()
324 		 * - The APIC IDs differ from the HyperTransport node IDs  in srat_detect_node()
337 		int ht_nodeid = c->topo.initial_apicid;  in srat_detect_node()
357 		 * per-processor PPR. Restrict SNP support on the known CPU models  in bsp_determine_snp()
361 		    c->x86 >= 0x19 && snp_probe_rmptable_info()) {  in bsp_determine_snp()
375 		if (c->x86 > 0x10 ||  in bsp_init_amd()
376 		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {  in bsp_init_amd()
385 	if (c->x86 == 0x15) {  in bsp_init_amd()
387 		u32 cpuid, assoc;  in bsp_init_amd()  local
390 		assoc	 = cpuid >> 16 & 0xff;  in bsp_init_amd()
391 		upperbit = ((cpuid >> 24) << 10) / assoc;  in bsp_init_amd()
393 		va_align.mask	  = (upperbit - 1) & PAGE_MASK;  in bsp_init_amd()
405 	    c->x86 >= 0x15 && c->x86 <= 0x17) {  in bsp_init_amd()
408 		switch (c->x86) {  in bsp_init_amd()
428 	switch (c->x86) {  in bsp_init_amd()
430 		switch (c->x86_model) {  in bsp_init_amd()
447 		switch (c->x86_model) {  in bsp_init_amd()
462 		switch (c->x86_model) {  in bsp_init_amd()
481 	WARN_ONCE(1, "Family 0x%x, model: 0x%x??\n", c->x86, c->x86_model);  in bsp_init_amd()
510 		 * will be a value above 32-bits this is still done for  in early_detect_mem_encrypt()
513 		c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;  in early_detect_mem_encrypt()
540 	if (c->x86 >= 0xf)  in early_init_amd()
543 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);  in early_init_amd()
546 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_amd()
547 	 * with P/T states and does not stop in deep C-states  in early_init_amd()
549 	if (c->x86_power & (1 << 8)) {  in early_init_amd()
555 	if (c->x86_power & BIT(12))  in early_init_amd()
559 	if (c->x86_power & BIT(14))  in early_init_amd()
566 	if (c->x86 == 5)  in early_init_amd()
567 		if (c->x86_model == 13 || c->x86_model == 9 ||  in early_init_amd()
568 		    (c->x86_model == 8 && c->x86_stepping >= 8))  in early_init_amd()
573 	 * ApicID can always be treated as an 8-bit value for AMD APIC versions  in early_init_amd()
579 		if (c->x86 > 0x16)  in early_init_amd()
581 		else if (c->x86 >= 0xf) {  in early_init_amd()
599 	/* F16h erratum 793, CVE-2013-6885 */  in early_init_amd()
600 	if (c->x86 == 0x16 && c->x86_model <= 0xf)  in early_init_amd()
606 		if (c->x86 == 0x17 && boot_cpu_has(X86_FEATURE_AMD_IBPB))  in early_init_amd()
608 		else if (c->x86 >= 0x19 && !wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) {  in early_init_amd()
630 	if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {  in init_amd_k8()
638 	if (!c->x86_model_id[0])  in init_amd_k8()
639 		strcpy(c->x86_model_id, "Hammer");  in init_amd_k8()
646 	 * Errata 63 for SH-B3 steppings  in init_amd_k8()
655 	 * used to select the proper idle routine and to enable the  in init_amd_k8()
659 	if (c->x86_model > 0x41 ||  in init_amd_k8()
660 	    (c->x86_model == 0x41 && c->x86_stepping >= 0x2))  in init_amd_k8()
687 	 * degradation for certain nested-paging guests. Prevent this conversion  in init_amd_gh()
699 	 * used to select the proper idle routine and to enable the  in init_amd_gh()
703 	if (c->x86_model > 0x2 ||  in init_amd_gh()
704 	    (c->x86_model == 0x2 && c->x86_stepping >= 0x1))  in init_amd_gh()
722 		return -EINVAL;  in rdrand_cmdline()
727 		return -EINVAL;  in rdrand_cmdline()
744 	 * The self-test can clear X86_FEATURE_RDRAND, so check for  in clear_rdrand_cpuid_bit()
783 	if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {  in init_amd_bd()
831 	 * suppresses non-branch predictions.  in init_spectral_chicken()
932 	switch (c->x86_model) {  in init_amd_zen4()
956 	if (c->x86 >= 0x10)  in init_amd()
964 	if (c->x86 < 6)  in init_amd()
967 	switch (c->x86) {  in init_amd()
982 	if (c->x86 >= 0x17)  in init_amd()
1000 	if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))  in init_amd()
1035 	if (c->x86 > 0x11)  in init_amd()
1053 	    (boot_cpu_has(X86_FEATURE_ZEN1) && c->x86_model > 0x2f))  in init_amd()
1059 	 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up  in init_amd()
1077 	if (c->x86 == 6) {  in amd_size_cache()
1079 		if (c->x86_model == 3 && c->x86_stepping == 0)  in amd_size_cache()
1082 		if (c->x86_model == 4 &&  in amd_size_cache()
1083 			(c->x86_stepping == 0 || c->x86_stepping == 1))  in amd_size_cache()
1095 	if (c->x86 < 0xf)  in cpu_detect_tlb_amd()
1098 	if (c->extended_cpuid_level < 0x80000006)  in cpu_detect_tlb_amd()
1110 	if (c->x86 == 0xf) {  in cpu_detect_tlb_amd()
1127 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {  in cpu_detect_tlb_amd()
1147 			  [7] = "486 DX/2-WB",
1149 			  [9] = "486 DX/4-WB",
1150 			  [14] = "Am5x86-WT",
1151 			  [15] = "Am5x86-WB"