23  *   before entering C3.
39 		 * Today all MP CPUs that support C3 share cache.  in acpi_processor_power_init_bm_check()
41 		 * entering C3 type state.  in acpi_processor_power_init_bm_check()
49 	 * is not required while entering C3 type state on  in acpi_processor_power_init_bm_check()
61 			 * core can keep cache coherence with each other while entering C3  in acpi_processor_power_init_bm_check()
64 			 * entering C3 type state.  in acpi_processor_power_init_bm_check()
70 			 * not required while entering C3 type state.  in acpi_processor_power_init_bm_check()
78 		 * All Zhaoxin CPUs that support C3 share cache.  in acpi_processor_power_init_bm_check()
80 		 * entering C3 type state.  in acpi_processor_power_init_bm_check()
86 		 * is not required while entering C3 type state.  in acpi_processor_power_init_bm_check()
92 		 * For all AMD Zen or newer CPUs that support C3, caches  in acpi_processor_power_init_bm_check()
93 		 * should not be flushed by software while entering C3  in acpi_processor_power_init_bm_check()
101 		 * required while entering C3 type state.  in acpi_processor_power_init_bm_check()
148 	/* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */  in acpi_processor_ffh_cstate_probe_cpu()