include/asm/tlbflush.h

1 /* SPDX-License-Identifier: GPL-2.0 */
15 #include <asm/processor-flags.h>
22 #define TLB_FLUSH_ALL	-1UL
75 	 * are on.  This means that it may not match current->active_mm,
80 	 * LOADED_MM_SWITCHING during the brief interrupts-off window
100 	 * This tells us to go invalidate all the non-loaded ctxs[]
103 	 * The current ctx was kept up-to-date as it ran and does not
138 	 * contain entries that are out-of-date as when that mm reached
146 	 * various bits of init code.  This is fine -- code that
158 	 *  - Actively using an mm.  Our CPU's bit will be set in
161 	 *  - Not using a real mm.  loaded_mm == &init_mm.  Our CPU's bit
164 	 *  - Lazily using a real mm.  loaded_mm != &init_mm, our bit
191  *  - flush_tlb_all() flushes all processes TLBs
192  *  - flush_tlb_mm(mm) flushes the specified mm context TLB's
193  *  - flush_tlb_page(vma, vmaddr) flushes one page
194  *  - flush_tlb_range(vma, start, end) flushes a range of pages
195  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
196  *  - flush_tlb_multi(cpumask, info) flushes TLBs on multiple cpus
199  * and page-granular flushes are available only on i486 and up.
205 	 * - Fully flush a single mm.  .mm will be set, .end will be
209 	 * - Partially flush a single mm.  .mm will be set, .start and
211 	 *   such that the changes between generation .new_tlb_gen-1 and
214 	 * - Fully flush all mms whose tlb_gens have been updated.  .mm
241 	flush_tlb_mm_range((vma)->vm_mm, start, end,			\
242 			   ((vma)->vm_flags & VM_HUGETLB)		\
254 	flush_tlb_mm_range(vma->vm_mm, a, a + PAGE_SIZE, PAGE_SHIFT, false);  in flush_tlb_page()
277 	return atomic64_inc_return(&mm->context.tlb_gen);  in inc_mm_tlb_gen()
285 	cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));  in arch_tlbbatch_add_pending()
286 	mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);  in arch_tlbbatch_add_pending()
302 	 * Only include flags that would not trigger spurious page-faults.  in pte_flags_need_flush()
303 	 * Non-present entries are not cached. Hardware would set the  in pte_flags_need_flush()
354 	/* !PRESENT -> * ; no need for flush */  in pte_needs_flush()
363 	 * check PTE flags; ignore access-bit; see comment in  in pte_needs_flush()
377 	/* !PRESENT -> * ; no need for flush */  in huge_pmd_needs_flush()
386 	 * check PMD flags; do not ignore access-bit; see  in huge_pmd_needs_flush()