40 #define P4_ESCR_EVENT(v)	((v) << P4_ESCR_EVENT_SHIFT)  argument
41 #define P4_ESCR_EMASK(v)	((v) << P4_ESCR_EVENTMASK_SHIFT)  argument
42 #define P4_ESCR_TAG(v)		((v) << P4_ESCR_TAG_SHIFT)  argument
62 #define P4_CCCR_THRESHOLD(v)		((v) << P4_CCCR_THRESHOLD_SHIFT)  argument
63 #define P4_CCCR_ESEL(v)			((v) << P4_CCCR_ESCR_SELECT_SHIFT)  argument
81 #define p4_config_pack_escr(v)		(((u64)(v)) << 32)  argument
82 #define p4_config_pack_cccr(v)		(((u64)(v)) & 0xffffffffULL)  argument
83 #define p4_config_unpack_escr(v)	(((u64)(v)) >> 32)  argument
84 #define p4_config_unpack_cccr(v)	(((u64)(v)) & 0xffffffffULL)  argument
86 #define p4_config_unpack_emask(v)			\  argument
88 		u32 t = p4_config_unpack_escr((v));	\
94 #define p4_config_unpack_event(v)			\  argument
96 		u32 t = p4_config_unpack_escr((v));	\
488 	 * MSR_P4_ALF_ESCR1:	14, 15, 17
524 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
530 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
536 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
542 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
548 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
554 	 * MSR_P4_RAT_ESCR1:	14, 15, 17
560 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
566 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
572 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
578 	 * MSR_P4_CRU_ESCR3:	14, 15, 17
584 	 * MSR_P4_CRU_ESCR1:	14, 15, 17
795  * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
800 #define p4_config_unpack_metric(v)	(((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)  argument
801 #define p4_config_unpack_pebs(v)	(((u64)(v)) & P4_PEBS_CONFIG_MASK)  argument
803 #define p4_config_pebs_has(v, mask)	(p4_config_unpack_pebs(v) & (mask))  argument
851  *    16-17: Active Thread