Lines Matching +full:low +full:-
1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "msr-index.h"
40 * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A"
46 /* Using 64-bit values saves one instruction clearing the high half of low */
47 #define DECLARE_ARGS(val, low, high) unsigned long low, high argument
48 #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) argument
49 #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) argument
51 #define DECLARE_ARGS(val, low, high) unsigned long long val argument
52 #define EAX_EDX_VAL(val, low, high) (val) argument
53 #define EAX_EDX_RET(val, low, high) "=A" (val) argument
60 #include <linux/tracepoint-defs.h>
78 * on them - those are *purely* for accessing MSRs and nothing more. So don't even
79 * think of extending them - you will be slapped with a stinking trout or a frozen
84 DECLARE_ARGS(val, low, high); in __rdmsr()
89 : EAX_EDX_RET(val, low, high) : "c" (msr)); in __rdmsr()
91 return EAX_EDX_VAL(val, low, high); in __rdmsr()
94 static __always_inline void __wrmsr(unsigned int msr, u32 low, u32 high) in __wrmsr() argument
99 : : "c" (msr), "a"(low), "d" (high) : "memory"); in __wrmsr()
109 #define native_wrmsr(msr, low, high) \ argument
110 __wrmsr(msr, low, high)
131 DECLARE_ARGS(val, low, high); in native_read_msr_safe()
136 : [err] "=r" (*err), EAX_EDX_RET(val, low, high) in native_read_msr_safe()
139 do_trace_read_msr(msr, EAX_EDX_VAL(val, low, high), *err); in native_read_msr_safe()
140 return EAX_EDX_VAL(val, low, high); in native_read_msr_safe()
145 native_write_msr(unsigned int msr, u32 low, u32 high) in native_write_msr() argument
147 __wrmsr(msr, low, high); in native_write_msr()
150 do_trace_write_msr(msr, ((u64)high << 32 | low), 0); in native_write_msr()
155 native_write_msr_safe(unsigned int msr, u32 low, u32 high) in native_write_msr_safe() argument
163 : "c" (msr), "0" (low), "d" (high) in native_write_msr_safe()
166 do_trace_write_msr(msr, ((u64)high << 32 | low), err); in native_write_msr_safe()
174 * rdtsc() - returns the current TSC without ordering constraints
176 * rdtsc() returns the result of RDTSC as a 64-bit integer. The
180 * results can be non-monotonic if compared on different CPUs.
184 DECLARE_ARGS(val, low, high); in rdtsc()
186 asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); in rdtsc()
188 return EAX_EDX_VAL(val, low, high); in rdtsc()
192 * rdtsc_ordered() - read the current TSC in program order
194 * rdtsc_ordered() returns the result of RDTSC as a 64-bit integer.
195 * It is ordered like a load to a global in-memory counter. It should
196 * be impossible to observe non-monotonic rdtsc_unordered() behavior
201 DECLARE_ARGS(val, low, high); in rdtsc_ordered()
220 : EAX_EDX_RET(val, low, high) in rdtsc_ordered()
224 return EAX_EDX_VAL(val, low, high); in rdtsc_ordered()
229 DECLARE_ARGS(val, low, high); in native_read_pmc()
231 asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); in native_read_pmc()
233 do_trace_rdpmc(counter, EAX_EDX_VAL(val, low, high), 0); in native_read_pmc()
234 return EAX_EDX_VAL(val, low, high); in native_read_pmc()
242 * Access to machine-specific registers (available on 586 and better only)
247 #define rdmsr(msr, low, high) \ argument
250 (void)((low) = (u32)__val); \
254 static inline void wrmsr(unsigned int msr, u32 low, u32 high) in wrmsr() argument
256 native_write_msr(msr, low, high); in wrmsr()
268 static inline int wrmsr_safe(unsigned int msr, u32 low, u32 high) in wrmsr_safe() argument
270 return native_write_msr_safe(msr, low, high); in wrmsr_safe()
274 #define rdmsr_safe(msr, low, high) \ argument
278 (*low) = (u32)__val; \
291 #define rdpmc(counter, low, high) \ argument
294 (low) = (u32)_l; \
305 /* Non-serializing WRMSR, when available. Falls back to a serializing WRMSR. */
318 * 64-bit version of wrmsr_safe():
367 rdmsr_on_cpu(0, msr_no, raw_cpu_ptr(&msrs->l), raw_cpu_ptr(&msrs->h)); in rdmsr_on_cpus()
372 wrmsr_on_cpu(0, msr_no, raw_cpu_read(msrs->l), raw_cpu_read(msrs->h)); in wrmsr_on_cpus()