Lines Matching +full:architecturally +full:- +full:defined

1 /* SPDX-License-Identifier: GPL-2.0 */
29 #define MCG_STATUS_SEAM_NR	BIT_ULL(12)  /* Machine check inside SEAM non-root mode */
49 /* AMD-specific bits */
58  *  - Deferred error interrupt type is specifiable by bank.
59  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
61  *  - TCC bit is present in MCx_STATUS.
69  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
72  * of uncorrected errors - so the F bit is deliberately skipped
77 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
78 #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
94 #define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
221 					     u64 lapic_id) { return -EINVAL; }  in apei_smca_report_x86_error()