Lines Matching +full:0 +full:x4650
7 #define PCI_DEVICE_ID_INTEL_SNB_IMC 0x0100
8 #define PCI_DEVICE_ID_INTEL_IVB_IMC 0x0154
9 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC 0x0150
10 #define PCI_DEVICE_ID_INTEL_HSW_IMC 0x0c00
11 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC 0x0a04
12 #define PCI_DEVICE_ID_INTEL_BDW_IMC 0x1604
13 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC 0x1904
14 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC 0x190c
15 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC 0x1900
16 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC 0x1910
17 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC 0x190f
18 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC 0x191f
19 #define PCI_DEVICE_ID_INTEL_SKL_E3_IMC 0x1918
20 #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC 0x590c
21 #define PCI_DEVICE_ID_INTEL_KBL_U_IMC 0x5904
22 #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC 0x5914
23 #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC 0x590f
24 #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC 0x591f
25 #define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC 0x5910
26 #define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC 0x5918
27 #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC 0x3ecc
28 #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC 0x3ed0
29 #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC 0x3e10
30 #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC 0x3ec4
31 #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC 0x3e0f
32 #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC 0x3e1f
33 #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC 0x3ec2
34 #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC 0x3e30
35 #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC 0x3e18
36 #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC 0x3ec6
37 #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC 0x3e31
38 #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC 0x3e33
39 #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC 0x3eca
40 #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC 0x3e32
41 #define PCI_DEVICE_ID_INTEL_AML_YD_IMC 0x590c
42 #define PCI_DEVICE_ID_INTEL_AML_YQ_IMC 0x590d
43 #define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC 0x3ed0
44 #define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC 0x3e34
45 #define PCI_DEVICE_ID_INTEL_WHL_UD_IMC 0x3e35
46 #define PCI_DEVICE_ID_INTEL_CML_H1_IMC 0x9b44
47 #define PCI_DEVICE_ID_INTEL_CML_H2_IMC 0x9b54
48 #define PCI_DEVICE_ID_INTEL_CML_H3_IMC 0x9b64
49 #define PCI_DEVICE_ID_INTEL_CML_U1_IMC 0x9b51
50 #define PCI_DEVICE_ID_INTEL_CML_U2_IMC 0x9b61
51 #define PCI_DEVICE_ID_INTEL_CML_U3_IMC 0x9b71
52 #define PCI_DEVICE_ID_INTEL_CML_S1_IMC 0x9b33
53 #define PCI_DEVICE_ID_INTEL_CML_S2_IMC 0x9b43
54 #define PCI_DEVICE_ID_INTEL_CML_S3_IMC 0x9b53
55 #define PCI_DEVICE_ID_INTEL_CML_S4_IMC 0x9b63
56 #define PCI_DEVICE_ID_INTEL_CML_S5_IMC 0x9b73
57 #define PCI_DEVICE_ID_INTEL_ICL_U_IMC 0x8a02
58 #define PCI_DEVICE_ID_INTEL_ICL_U2_IMC 0x8a12
59 #define PCI_DEVICE_ID_INTEL_TGL_U1_IMC 0x9a02
60 #define PCI_DEVICE_ID_INTEL_TGL_U2_IMC 0x9a04
61 #define PCI_DEVICE_ID_INTEL_TGL_U3_IMC 0x9a12
62 #define PCI_DEVICE_ID_INTEL_TGL_U4_IMC 0x9a14
63 #define PCI_DEVICE_ID_INTEL_TGL_H_IMC 0x9a36
64 #define PCI_DEVICE_ID_INTEL_RKL_1_IMC 0x4c43
65 #define PCI_DEVICE_ID_INTEL_RKL_2_IMC 0x4c53
66 #define PCI_DEVICE_ID_INTEL_ADL_1_IMC 0x4660
67 #define PCI_DEVICE_ID_INTEL_ADL_2_IMC 0x4641
68 #define PCI_DEVICE_ID_INTEL_ADL_3_IMC 0x4601
69 #define PCI_DEVICE_ID_INTEL_ADL_4_IMC 0x4602
70 #define PCI_DEVICE_ID_INTEL_ADL_5_IMC 0x4609
71 #define PCI_DEVICE_ID_INTEL_ADL_6_IMC 0x460a
72 #define PCI_DEVICE_ID_INTEL_ADL_7_IMC 0x4621
73 #define PCI_DEVICE_ID_INTEL_ADL_8_IMC 0x4623
74 #define PCI_DEVICE_ID_INTEL_ADL_9_IMC 0x4629
75 #define PCI_DEVICE_ID_INTEL_ADL_10_IMC 0x4637
76 #define PCI_DEVICE_ID_INTEL_ADL_11_IMC 0x463b
77 #define PCI_DEVICE_ID_INTEL_ADL_12_IMC 0x4648
78 #define PCI_DEVICE_ID_INTEL_ADL_13_IMC 0x4649
79 #define PCI_DEVICE_ID_INTEL_ADL_14_IMC 0x4650
80 #define PCI_DEVICE_ID_INTEL_ADL_15_IMC 0x4668
81 #define PCI_DEVICE_ID_INTEL_ADL_16_IMC 0x4670
82 #define PCI_DEVICE_ID_INTEL_ADL_17_IMC 0x4614
83 #define PCI_DEVICE_ID_INTEL_ADL_18_IMC 0x4617
84 #define PCI_DEVICE_ID_INTEL_ADL_19_IMC 0x4618
85 #define PCI_DEVICE_ID_INTEL_ADL_20_IMC 0x461B
86 #define PCI_DEVICE_ID_INTEL_ADL_21_IMC 0x461C
87 #define PCI_DEVICE_ID_INTEL_RPL_1_IMC 0xA700
88 #define PCI_DEVICE_ID_INTEL_RPL_2_IMC 0xA702
89 #define PCI_DEVICE_ID_INTEL_RPL_3_IMC 0xA706
90 #define PCI_DEVICE_ID_INTEL_RPL_4_IMC 0xA709
91 #define PCI_DEVICE_ID_INTEL_RPL_5_IMC 0xA701
92 #define PCI_DEVICE_ID_INTEL_RPL_6_IMC 0xA703
93 #define PCI_DEVICE_ID_INTEL_RPL_7_IMC 0xA704
94 #define PCI_DEVICE_ID_INTEL_RPL_8_IMC 0xA705
95 #define PCI_DEVICE_ID_INTEL_RPL_9_IMC 0xA706
96 #define PCI_DEVICE_ID_INTEL_RPL_10_IMC 0xA707
97 #define PCI_DEVICE_ID_INTEL_RPL_11_IMC 0xA708
98 #define PCI_DEVICE_ID_INTEL_RPL_12_IMC 0xA709
99 #define PCI_DEVICE_ID_INTEL_RPL_13_IMC 0xA70a
100 #define PCI_DEVICE_ID_INTEL_RPL_14_IMC 0xA70b
101 #define PCI_DEVICE_ID_INTEL_RPL_15_IMC 0xA715
102 #define PCI_DEVICE_ID_INTEL_RPL_16_IMC 0xA716
103 #define PCI_DEVICE_ID_INTEL_RPL_17_IMC 0xA717
104 #define PCI_DEVICE_ID_INTEL_RPL_18_IMC 0xA718
105 #define PCI_DEVICE_ID_INTEL_RPL_19_IMC 0xA719
106 #define PCI_DEVICE_ID_INTEL_RPL_20_IMC 0xA71A
107 #define PCI_DEVICE_ID_INTEL_RPL_21_IMC 0xA71B
108 #define PCI_DEVICE_ID_INTEL_RPL_22_IMC 0xA71C
109 #define PCI_DEVICE_ID_INTEL_RPL_23_IMC 0xA728
110 #define PCI_DEVICE_ID_INTEL_RPL_24_IMC 0xA729
111 #define PCI_DEVICE_ID_INTEL_RPL_25_IMC 0xA72A
112 #define PCI_DEVICE_ID_INTEL_MTL_1_IMC 0x7d00
113 #define PCI_DEVICE_ID_INTEL_MTL_2_IMC 0x7d01
114 #define PCI_DEVICE_ID_INTEL_MTL_3_IMC 0x7d02
115 #define PCI_DEVICE_ID_INTEL_MTL_4_IMC 0x7d05
116 #define PCI_DEVICE_ID_INTEL_MTL_5_IMC 0x7d10
117 #define PCI_DEVICE_ID_INTEL_MTL_6_IMC 0x7d14
118 #define PCI_DEVICE_ID_INTEL_MTL_7_IMC 0x7d15
119 #define PCI_DEVICE_ID_INTEL_MTL_8_IMC 0x7d16
120 #define PCI_DEVICE_ID_INTEL_MTL_9_IMC 0x7d21
121 #define PCI_DEVICE_ID_INTEL_MTL_10_IMC 0x7d22
122 #define PCI_DEVICE_ID_INTEL_MTL_11_IMC 0x7d23
123 #define PCI_DEVICE_ID_INTEL_MTL_12_IMC 0x7d24
124 #define PCI_DEVICE_ID_INTEL_MTL_13_IMC 0x7d28
130 .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0), \
134 #define SNB_UNC_CTL_EV_SEL_MASK 0x000000ff
135 #define SNB_UNC_CTL_UMASK_MASK 0x0000ff00
139 #define SNB_UNC_CTL_CMASK_MASK 0x1f000000
140 #define NHM_UNC_CTL_CMASK_MASK 0xff000000
141 #define NHM_UNC_FIXED_CTR_CTL_EN (1 << 0)
156 #define SNB_UNC_PERF_GLOBAL_CTL 0x391
157 #define SNB_UNC_FIXED_CTR_CTRL 0x394
158 #define SNB_UNC_FIXED_CTR 0x395
165 #define SNB_UNC_CBO_0_PERFEVTSEL0 0x700
166 #define SNB_UNC_CBO_0_PER_CTR0 0x706
167 #define SNB_UNC_CBO_MSR_OFFSET 0x10
170 #define SNB_UNC_ARB_PER_CTR0 0x3b0
171 #define SNB_UNC_ARB_PERFEVTSEL0 0x3b2
172 #define SNB_UNC_ARB_MSR_OFFSET 0x10
175 #define NHM_UNC_PERF_GLOBAL_CTL 0x391
176 #define NHM_UNC_FIXED_CTR 0x394
177 #define NHM_UNC_FIXED_CTR_CTRL 0x395
184 #define NHM_UNC_PERFEVTSEL0 0x3c0
185 #define NHM_UNC_UNCORE_PMC0 0x3b0
188 #define SKL_UNC_PERF_GLOBAL_CTL 0xe01
192 #define ICL_UNC_CBO_CONFIG 0x396
193 #define ICL_UNC_NUM_CBO_MASK 0xf
194 #define ICL_UNC_CBO_0_PER_CTR0 0x702
195 #define ICL_UNC_CBO_MSR_OFFSET 0x8
198 #define ICL_UNC_ARB_PER_CTR 0x3b1
199 #define ICL_UNC_ARB_PERFEVTSEL 0x3b3
202 #define ADL_UNC_PERF_GLOBAL_CTL 0x2ff0
203 #define ADL_UNC_FIXED_CTR_CTRL 0x2fde
204 #define ADL_UNC_FIXED_CTR 0x2fdf
207 #define ADL_UNC_CBO_0_PER_CTR0 0x2002
208 #define ADL_UNC_CBO_0_PERFEVTSEL0 0x2000
209 #define ADL_UNC_CTL_THRESHOLD 0x3f000000
217 #define ADL_UNC_ARB_PER_CTR0 0x2FD2
218 #define ADL_UNC_ARB_PERFEVTSEL0 0x2FD0
219 #define ADL_UNC_ARB_MSR_OFFSET 0x8
222 #define MTL_UNC_CBO_0_PER_CTR0 0x2448
223 #define MTL_UNC_CBO_0_PERFEVTSEL0 0x2442
226 #define MTL_UNC_HAC_ARB_CTR 0x2018
227 #define MTL_UNC_HAC_ARB_CTRL 0x2012
230 #define MTL_UNC_ARB_CTR 0x2418
231 #define MTL_UNC_ARB_CTRL 0x2412
234 #define MTL_UNC_CNCU_FIXED_CTR 0x2408
235 #define MTL_UNC_CNCU_FIXED_CTRL 0x2402
236 #define MTL_UNC_CNCU_BOX_CTL 0x240e
239 #define MTL_UNC_SNCU_FIXED_CTR 0x2008
240 #define MTL_UNC_SNCU_FIXED_CTRL 0x2002
241 #define MTL_UNC_SNCU_BOX_CTL 0x200e
244 #define MTL_UNC_HBO_CTR 0x2048
245 #define MTL_UNC_HBO_CTRL 0x2042
247 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
270 wrmsrl(event->hw.config_base, 0); in snb_uncore_msr_disable_event()
275 if (box->pmu->pmu_idx == 0) { in snb_uncore_msr_init_box()
289 if (box->pmu->pmu_idx == 0) in snb_uncore_msr_exit_box()
290 wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0); in snb_uncore_msr_exit_box()
294 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
322 UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
323 UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
374 if (box->pmu->pmu_idx == 0) { in skl_uncore_msr_init_box()
392 if (box->pmu->pmu_idx == 0) in skl_uncore_msr_exit_box()
393 wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0); in skl_uncore_msr_exit_box()
456 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff"),
527 if (box->pmu->pmu_idx == 0) in rkl_uncore_msr_init_box()
543 if (box->pmu->pmu_idx == 0) in adl_uncore_msr_init_box()
554 if (box->pmu->pmu_idx == 0) in adl_uncore_msr_disable_box()
555 wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0); in adl_uncore_msr_disable_box()
560 if (box->pmu->pmu_idx == 0) in adl_uncore_msr_exit_box()
561 wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0); in adl_uncore_msr_exit_box()
756 #define LNL_UNC_MSR_GLOBAL_CTL 0x240e
760 if (box->pmu->pmu_idx == 0) in lnl_uncore_msr_init_box()
783 INTEL_UNCORE_EVENT_DESC(data_reads, "event=0x01"),
787 INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
791 INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"),
795 INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"),
799 INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"),
806 #define SNB_UNCORE_PCI_IMC_EVENT_MASK 0xff
807 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET 0x48
810 #define SNB_UNCORE_PCI_IMC_MAP_SIZE 0x6000
812 #define SNB_UNCORE_PCI_IMC_DATA_READS 0x1
813 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE 0x5050
814 #define SNB_UNCORE_PCI_IMC_DATA_WRITES 0x2
815 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
819 #define SNB_UNCORE_PCI_IMC_GT_REQUESTS 0x3
820 #define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040
821 #define SNB_UNCORE_PCI_IMC_IA_REQUESTS 0x4
822 #define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044
823 #define SNB_UNCORE_PCI_IMC_IO_REQUESTS 0x5
824 #define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048
827 SNB_PCI_UNCORE_IMC_DATA_READS = 0,
838 0x0, 0x0, 1, 32 },
840 0x0, 0x0, 1, 32 },
842 0x0, 0x0, 1, 32 },
844 0x0, 0x0, 1, 32 },
846 0x0, 0x0, 1, 32 },
913 if (pmu->func_id < 0) in snb_uncore_imc_event_init()
928 if (event->cpu < 0) in snb_uncore_imc_event_init()
936 if (!box || box->cpu < 0) in snb_uncore_imc_event_init()
945 event->hw.last_tag = ~0ULL; in snb_uncore_imc_event_init()
981 event->hw.config = ((cfg - 1) << 8) | 0x10ff; in snb_uncore_imc_event_init()
985 return 0; in snb_uncore_imc_event_init()
990 return 0; in snb_uncore_imc_hw_config()
1013 map->pbus_to_dieid[bus] = 0; in snb_pci2phy_map_init()
1018 return 0; in snb_pci2phy_map_init()
1261 if (ret == 0) in imc_uncore_find_dev()
1277 return 0; in imc_uncore_pci_init()
1309 wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0); in nhm_uncore_msr_disable_box()
1342 INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
1343 INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any, "event=0x2f,umask=0x0f"),
1344 INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any, "event=0x2c,umask=0x0f"),
1345 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads, "event=0x20,umask=0x01"),
1346 INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes, "event=0x20,umask=0x02"),
1347 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads, "event=0x20,umask=0x04"),
1348 INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
1349 INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads, "event=0x20,umask=0x10"),
1350 INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes, "event=0x20,umask=0x20"),
1468 [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0x5040, 0x0, 0x0, 1, 64 },
1469 [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0x5058, 0x0, 0x0, 1, 64 },
1470 [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0x50A0, 0x0, 0x0, 1, 64 },
1474 [TGL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0xd840, 0x0, 0x0, 1, 64 },
1475 [TGL_MMIO_UNCORE_IMC_DATA_READ] = { 0xd858, 0x0, 0x0, 1, 64 },
1476 [TGL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0xd8A0, 0x0, 0x0, 1, 64 },
1480 INTEL_UNCORE_EVENT_DESC(data_total, "event=0xff,umask=0x10"),
1484 INTEL_UNCORE_EVENT_DESC(data_read, "event=0xff,umask=0x20"),
1488 INTEL_UNCORE_EVENT_DESC(data_write, "event=0xff,umask=0x30"),
1509 mc_dev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); in tgl_uncore_get_mc_dev()
1514 #define TGL_UNCORE_MMIO_IMC_MEM_OFFSET 0x10000
1515 #define TGL_UNCORE_PCI_IMC_MAP_SIZE 0xe000
1534 if (!(bar & BIT(0))) { in uncore_get_box_mmio_addr()
1535 pr_warn("perf uncore: BAR 0x%x is disabled. Failed to map %s counters.\n", in uncore_get_box_mmio_addr()
1540 bar &= ~BIT(0); in uncore_get_box_mmio_addr()
1566 __uncore_imc_init_box(box, 0); in tgl_uncore_imc_freerunning_init_box()
1618 #define ADL_UNCORE_IMC_BASE 0xd900
1619 #define ADL_UNCORE_IMC_MAP_SIZE 0x200
1620 #define ADL_UNCORE_IMC_CTR 0xe8
1621 #define ADL_UNCORE_IMC_CTRL 0xd0
1622 #define ADL_UNCORE_IMC_GLOBAL_CTL 0xc0
1623 #define ADL_UNCORE_IMC_BOX_CTL 0xc4
1624 #define ADL_UNCORE_IMC_FREERUNNING_BASE 0xd800
1625 #define ADL_UNCORE_IMC_FREERUNNING_MAP_SIZE 0x100
1627 #define ADL_UNCORE_IMC_CTL_FRZ (1 << 0)
1655 writel(0, box->io_addr + uncore_mmio_box_ctl(box)); in adl_uncore_mmio_enable_box()
1671 #define ADL_UNC_CTL_CHMASK_MASK 0x00000f00
1697 .mmio_offset = 0,
1711 [ADL_MMIO_UNCORE_IMC_DATA_TOTAL] = { 0x40, 0x0, 0x0, 1, 64 },
1712 [ADL_MMIO_UNCORE_IMC_DATA_READ] = { 0x58, 0x0, 0x0, 1, 64 },
1713 [ADL_MMIO_UNCORE_IMC_DATA_WRITE] = { 0xA0, 0x0, 0x0, 1, 64 },
1754 #define LNL_UNCORE_PCI_SAFBAR_OFFSET 0x68
1755 #define LNL_UNCORE_MAP_SIZE 0x1000
1756 #define LNL_UNCORE_SNCU_BASE 0xE4B000
1757 #define LNL_UNCORE_SNCU_CTR 0x390
1758 #define LNL_UNCORE_SNCU_CTRL 0x398
1759 #define LNL_UNCORE_SNCU_BOX_CTL 0x380
1760 #define LNL_UNCORE_GLOBAL_CTL 0x700
1761 #define LNL_UNCORE_HBO_BASE 0xE54000
1763 #define LNL_UNCORE_HBO_CTR 0x570
1764 #define LNL_UNCORE_HBO_CTRL 0x550
1765 #define LNL_UNCORE_HBO_BOX_CTL 0x548
1767 #define LNL_UNC_CTL_THRESHOLD 0xff000000
1818 0); in lnl_uncore_sncu_init_box()