Lines Matching +full:use +full:- +full:rtm
1 // SPDX-License-Identifier: GPL-2.0
203 OP_LH | LEVEL(MSC) | P(SNOOP, NONE), /* 0x10: Memory-side Cache Hit */
263 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) in precise_datala_hsw()
265 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) in precise_datala_hsw()
276 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { in precise_datala_hsw()
302 /* Retrieve the latency data for e-core of ADL */
308 WARN_ON_ONCE(hybrid_pmu(event->pmu)->pmu_type == hybrid_big); in __grt_latency_data()
311 val = hybrid_var(event->pmu, pebs_data_source)[dse]; in __grt_latency_data()
334 /* Retrieve the latency data for e-core of MTL */
355 val = hybrid_var(event->pmu, pebs_data_source)[status & PERF_PEBS_DATA_SOURCE_MASK]; in lnc_latency_data()
375 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) in lnc_latency_data()
383 struct x86_hybrid_pmu *pmu = hybrid_pmu(event->pmu); in lnl_latency_data()
385 if (pmu->pmu_type == hybrid_small) in lnl_latency_data()
399 * use the mapping table for bit 0-3 in load_latency_data()
401 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; in load_latency_data()
449 * use the mapping table for bit 0-3 in store_latency_data()
451 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse]; in store_latency_data()
562 * This is a cross-CPU update of the cpu_entry_area, we must shoot down in ds_update_cea()
601 struct debug_store *ds = hwev->ds; in alloc_pebs_buffer()
611 return -ENOMEM; in alloc_pebs_buffer()
621 return -ENOMEM; in alloc_pebs_buffer()
625 hwev->ds_pebs_vaddr = buffer; in alloc_pebs_buffer()
627 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in alloc_pebs_buffer()
628 ds->pebs_buffer_base = (unsigned long) cea; in alloc_pebs_buffer()
630 ds->pebs_index = ds->pebs_buffer_base; in alloc_pebs_buffer()
632 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; in alloc_pebs_buffer()
648 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in release_pebs_buffer()
650 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
651 hwev->ds_pebs_vaddr = NULL; in release_pebs_buffer()
657 struct debug_store *ds = hwev->ds; in alloc_bts_buffer()
667 return -ENOMEM; in alloc_bts_buffer()
669 hwev->ds_bts_vaddr = buffer; in alloc_bts_buffer()
671 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in alloc_bts_buffer()
672 ds->bts_buffer_base = (unsigned long) cea; in alloc_bts_buffer()
674 ds->bts_index = ds->bts_buffer_base; in alloc_bts_buffer()
676 ds->bts_absolute_maximum = ds->bts_buffer_base + in alloc_bts_buffer()
678 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - in alloc_bts_buffer()
692 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in release_bts_buffer()
694 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); in release_bts_buffer()
695 hwev->ds_bts_vaddr = NULL; in release_bts_buffer()
700 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; in alloc_ds_buffer()
832 if (!cpuc->ds) in intel_pmu_disable_bts()
847 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_bts_buffer()
853 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; in intel_pmu_drain_bts_buffer()
867 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
868 top = (struct bts_record *)(unsigned long)ds->bts_index; in intel_pmu_drain_bts_buffer()
875 ds->bts_index = ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
877 perf_sample_data_init(&data, 0, event->hw.last_period); in intel_pmu_drain_bts_buffer()
895 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
896 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
910 header.size * (top - base - skip))) in intel_pmu_drain_bts_buffer()
915 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
916 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
919 data.ip = at->from; in intel_pmu_drain_bts_buffer()
920 data.addr = at->to; in intel_pmu_drain_bts_buffer()
928 event->hw.interrupts++; in intel_pmu_drain_bts_buffer()
929 event->pending_kill = POLL_IN; in intel_pmu_drain_bts_buffer()
1205 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints); in intel_pebs_constraints()
1208 if (!event->attr.precise_ip) in intel_pebs_constraints()
1213 if (constraint_match(c, event->hw.config)) { in intel_pebs_constraints()
1214 event->hw.flags |= c->flags; in intel_pebs_constraints()
1231 * We need the sched_task callback even for per-cpu events when we use
1237 if (cpuc->n_pebs == cpuc->n_pebs_via_pt) in pebs_needs_sched_cb()
1240 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); in pebs_needs_sched_cb()
1253 struct debug_store *ds = cpuc->ds; in pebs_update_threshold()
1254 int max_pebs_events = intel_pmu_max_num_pebs(cpuc->pmu); in pebs_update_threshold()
1258 if (cpuc->n_pebs_via_pt) in pebs_update_threshold()
1262 reserved = max_pebs_events + x86_pmu_max_num_counters_fixed(cpuc->pmu); in pebs_update_threshold()
1266 if (cpuc->n_pebs == cpuc->n_large_pebs) { in pebs_update_threshold()
1267 threshold = ds->pebs_absolute_maximum - in pebs_update_threshold()
1268 reserved * cpuc->pebs_record_size; in pebs_update_threshold()
1270 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size; in pebs_update_threshold()
1273 ds->pebs_interrupt_threshold = threshold; in pebs_update_threshold()
1279 u64 pebs_data_cfg = cpuc->pebs_data_cfg; in adaptive_pebs_record_size_update()
1291 cpuc->pebs_record_size = sz; in adaptive_pebs_record_size_update()
1302 struct perf_event_attr *attr = &event->attr; in pebs_update_adaptive_cfg()
1303 u64 sample_type = attr->sample_type; in pebs_update_adaptive_cfg()
1308 attr->precise_ip > 1) in pebs_update_adaptive_cfg()
1318 * + For RTM TSX weight we need GPRs for the abort code. in pebs_update_adaptive_cfg()
1321 (attr->sample_regs_intr & PEBS_GP_REGS); in pebs_update_adaptive_cfg()
1324 ((attr->config & INTEL_ARCH_EVENT_MASK) == in pebs_update_adaptive_cfg()
1327 if (gprs || (attr->precise_ip < 2) || tsx_weight) in pebs_update_adaptive_cfg()
1331 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK)) in pebs_update_adaptive_cfg()
1340 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); in pebs_update_adaptive_cfg()
1350 struct pmu *pmu = event->pmu; in pebs_update_state()
1354 * During removal, ->pebs_data_cfg is still valid for in pebs_update_state()
1357 if ((cpuc->n_pebs == 1) && add) in pebs_update_state()
1358 cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW; in pebs_update_state()
1366 cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW; in pebs_update_state()
1380 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) in pebs_update_state()
1381 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW; in pebs_update_state()
1388 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_add()
1391 cpuc->n_pebs++; in intel_pmu_pebs_add()
1392 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_add()
1393 cpuc->n_large_pebs++; in intel_pmu_pebs_add()
1394 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) in intel_pmu_pebs_add()
1395 cpuc->n_pebs_via_pt++; in intel_pmu_pebs_add()
1407 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK)) in intel_pmu_pebs_via_pt_disable()
1408 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK; in intel_pmu_pebs_via_pt_disable()
1414 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_via_pt_enable()
1415 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_via_pt_enable()
1416 u64 value = ds->pebs_event_reset[hwc->idx]; in intel_pmu_pebs_via_pt_enable()
1418 unsigned int idx = hwc->idx; in intel_pmu_pebs_via_pt_enable()
1423 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) in intel_pmu_pebs_via_pt_enable()
1424 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD; in intel_pmu_pebs_via_pt_enable()
1426 cpuc->pebs_enabled |= PEBS_OUTPUT_PT; in intel_pmu_pebs_via_pt_enable()
1428 if (hwc->idx >= INTEL_PMC_IDX_FIXED) { in intel_pmu_pebs_via_pt_enable()
1430 idx = hwc->idx - INTEL_PMC_IDX_FIXED; in intel_pmu_pebs_via_pt_enable()
1432 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx]; in intel_pmu_pebs_via_pt_enable()
1434 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx]; in intel_pmu_pebs_via_pt_enable()
1441 if (cpuc->n_pebs == cpuc->n_large_pebs && in intel_pmu_drain_large_pebs()
1442 cpuc->n_pebs != cpuc->n_pebs_via_pt) in intel_pmu_drain_large_pebs()
1449 u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW; in intel_pmu_pebs_enable()
1450 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_enable()
1451 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_enable()
1452 unsigned int idx = hwc->idx; in intel_pmu_pebs_enable()
1454 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_enable()
1456 cpuc->pebs_enabled |= 1ULL << hwc->idx; in intel_pmu_pebs_enable()
1458 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) in intel_pmu_pebs_enable()
1459 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); in intel_pmu_pebs_enable()
1460 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_enable()
1461 cpuc->pebs_enabled |= 1ULL << 63; in intel_pmu_pebs_enable()
1464 hwc->config |= ICL_EVENTSEL_ADAPTIVE; in intel_pmu_pebs_enable()
1465 if (pebs_data_cfg != cpuc->active_pebs_data_cfg) { in intel_pmu_pebs_enable()
1474 cpuc->active_pebs_data_cfg = pebs_data_cfg; in intel_pmu_pebs_enable()
1477 if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) { in intel_pmu_pebs_enable()
1478 cpuc->pebs_data_cfg = pebs_data_cfg; in intel_pmu_pebs_enable()
1484 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()
1486 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()
1490 * Use auto-reload if possible to save a MSR write in the PMI. in intel_pmu_pebs_enable()
1493 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in intel_pmu_pebs_enable()
1494 ds->pebs_event_reset[idx] = in intel_pmu_pebs_enable()
1495 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
1497 ds->pebs_event_reset[idx] = 0; in intel_pmu_pebs_enable()
1506 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_del()
1509 cpuc->n_pebs--; in intel_pmu_pebs_del()
1510 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_del()
1511 cpuc->n_large_pebs--; in intel_pmu_pebs_del()
1512 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) in intel_pmu_pebs_del()
1513 cpuc->n_pebs_via_pt--; in intel_pmu_pebs_del()
1521 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_disable()
1525 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); in intel_pmu_pebs_disable()
1527 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && in intel_pmu_pebs_disable()
1529 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); in intel_pmu_pebs_disable()
1530 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_disable()
1531 cpuc->pebs_enabled &= ~(1ULL << 63); in intel_pmu_pebs_disable()
1535 if (cpuc->enabled) in intel_pmu_pebs_disable()
1536 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1538 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_disable()
1545 if (cpuc->pebs_enabled) in intel_pmu_pebs_enable_all()
1546 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
1553 if (cpuc->pebs_enabled) in intel_pmu_pebs_disable_all()
1560 unsigned long from = cpuc->lbr_entries[0].from; in intel_pmu_pebs_fixup_ip()
1561 unsigned long old_to, to = cpuc->lbr_entries[0].to; in intel_pmu_pebs_fixup_ip()
1562 unsigned long ip = regs->ip; in intel_pmu_pebs_fixup_ip()
1576 if (!cpuc->lbr_stack.nr || !from || !to) in intel_pmu_pebs_fixup_ip()
1589 if ((ip - to) > PEBS_FIXUP_SIZE) in intel_pmu_pebs_fixup_ip()
1600 size = ip - to; in intel_pmu_pebs_fixup_ip()
1635 size -= insn.length; in intel_pmu_pebs_fixup_ip()
1663 /* For RTM XABORTs also log the abort code from AX */ in intel_get_tsx_transaction()
1672 return ((struct pebs_record_nhm *)n)->status; in get_pebs_status()
1673 return ((struct pebs_basic *)n)->applicable_counters; in get_pebs_status()
1684 int fl = event->hw.flags; in get_data_src()
1704 /* Converting to a user-defined clock is not supported yet. */ in setup_pebs_time()
1705 if (event->attr.use_clockid != 0) in setup_pebs_time()
1717 data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset; in setup_pebs_time()
1718 data->sample_flags |= PERF_SAMPLE_TIME; in setup_pebs_time()
1742 sample_type = event->attr.sample_type; in setup_pebs_fixed_sample_data()
1743 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT; in setup_pebs_fixed_sample_data()
1745 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_fixed_sample_data()
1747 data->period = event->hw.last_period; in setup_pebs_fixed_sample_data()
1750 * Use latency for weight (only avail with PEBS-LL) in setup_pebs_fixed_sample_data()
1753 data->weight.full = pebs->lat; in setup_pebs_fixed_sample_data()
1754 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; in setup_pebs_fixed_sample_data()
1761 data->data_src.val = get_data_src(event, pebs->dse); in setup_pebs_fixed_sample_data()
1762 data->sample_flags |= PERF_SAMPLE_DATA_SRC; in setup_pebs_fixed_sample_data()
1766 * We must however always use iregs for the unwinder to stay sane; the in setup_pebs_fixed_sample_data()
1775 * We use the interrupt regs as a base because the PEBS record does not in setup_pebs_fixed_sample_data()
1788 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1791 regs->ax = pebs->ax; in setup_pebs_fixed_sample_data()
1792 regs->bx = pebs->bx; in setup_pebs_fixed_sample_data()
1793 regs->cx = pebs->cx; in setup_pebs_fixed_sample_data()
1794 regs->dx = pebs->dx; in setup_pebs_fixed_sample_data()
1795 regs->si = pebs->si; in setup_pebs_fixed_sample_data()
1796 regs->di = pebs->di; in setup_pebs_fixed_sample_data()
1798 regs->bp = pebs->bp; in setup_pebs_fixed_sample_data()
1799 regs->sp = pebs->sp; in setup_pebs_fixed_sample_data()
1802 regs->r8 = pebs->r8; in setup_pebs_fixed_sample_data()
1803 regs->r9 = pebs->r9; in setup_pebs_fixed_sample_data()
1804 regs->r10 = pebs->r10; in setup_pebs_fixed_sample_data()
1805 regs->r11 = pebs->r11; in setup_pebs_fixed_sample_data()
1806 regs->r12 = pebs->r12; in setup_pebs_fixed_sample_data()
1807 regs->r13 = pebs->r13; in setup_pebs_fixed_sample_data()
1808 regs->r14 = pebs->r14; in setup_pebs_fixed_sample_data()
1809 regs->r15 = pebs->r15; in setup_pebs_fixed_sample_data()
1813 if (event->attr.precise_ip > 1) { in setup_pebs_fixed_sample_data()
1816 * (real IP) which fixes the off-by-1 skid in hardware. in setup_pebs_fixed_sample_data()
1817 * Use it when precise_ip >= 2 : in setup_pebs_fixed_sample_data()
1820 set_linear_ip(regs, pebs->real_ip); in setup_pebs_fixed_sample_data()
1821 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1823 /* Otherwise, use PEBS off-by-1 IP: */ in setup_pebs_fixed_sample_data()
1824 set_linear_ip(regs, pebs->ip); in setup_pebs_fixed_sample_data()
1827 * With precise_ip >= 2, try to fix up the off-by-1 IP in setup_pebs_fixed_sample_data()
1829 * corrects regs->ip and calls set_linear_ip() on regs: in setup_pebs_fixed_sample_data()
1832 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1836 * When precise_ip == 1, return the PEBS off-by-1 IP, in setup_pebs_fixed_sample_data()
1839 set_linear_ip(regs, pebs->ip); in setup_pebs_fixed_sample_data()
1845 data->addr = pebs->dla; in setup_pebs_fixed_sample_data()
1846 data->sample_flags |= PERF_SAMPLE_ADDR; in setup_pebs_fixed_sample_data()
1852 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning); in setup_pebs_fixed_sample_data()
1853 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; in setup_pebs_fixed_sample_data()
1856 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning, in setup_pebs_fixed_sample_data()
1857 pebs->ax); in setup_pebs_fixed_sample_data()
1858 data->sample_flags |= PERF_SAMPLE_TRANSACTION; in setup_pebs_fixed_sample_data()
1863 * v3 supplies an accurate time stamp, so we use that in setup_pebs_fixed_sample_data()
1869 setup_pebs_time(event, data, pebs->tsc); in setup_pebs_fixed_sample_data()
1872 perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); in setup_pebs_fixed_sample_data()
1878 regs->ax = gprs->ax; in adaptive_pebs_save_regs()
1879 regs->bx = gprs->bx; in adaptive_pebs_save_regs()
1880 regs->cx = gprs->cx; in adaptive_pebs_save_regs()
1881 regs->dx = gprs->dx; in adaptive_pebs_save_regs()
1882 regs->si = gprs->si; in adaptive_pebs_save_regs()
1883 regs->di = gprs->di; in adaptive_pebs_save_regs()
1884 regs->bp = gprs->bp; in adaptive_pebs_save_regs()
1885 regs->sp = gprs->sp; in adaptive_pebs_save_regs()
1887 regs->r8 = gprs->r8; in adaptive_pebs_save_regs()
1888 regs->r9 = gprs->r9; in adaptive_pebs_save_regs()
1889 regs->r10 = gprs->r10; in adaptive_pebs_save_regs()
1890 regs->r11 = gprs->r11; in adaptive_pebs_save_regs()
1891 regs->r12 = gprs->r12; in adaptive_pebs_save_regs()
1892 regs->r13 = gprs->r13; in adaptive_pebs_save_regs()
1893 regs->r14 = gprs->r14; in adaptive_pebs_save_regs()
1894 regs->r15 = gprs->r15; in adaptive_pebs_save_regs()
1924 perf_regs->xmm_regs = NULL; in setup_pebs_adaptive_sample_data()
1926 sample_type = event->attr.sample_type; in setup_pebs_adaptive_sample_data()
1927 format_size = basic->format_size; in setup_pebs_adaptive_sample_data()
1928 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_adaptive_sample_data()
1929 data->period = event->hw.last_period; in setup_pebs_adaptive_sample_data()
1931 setup_pebs_time(event, data, basic->tsc); in setup_pebs_adaptive_sample_data()
1934 * We must however always use iregs for the unwinder to stay sane; the in setup_pebs_adaptive_sample_data()
1944 set_linear_ip(regs, basic->ip); in setup_pebs_adaptive_sample_data()
1945 regs->flags = PERF_EFLAGS_EXACT; in setup_pebs_adaptive_sample_data()
1949 data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK; in setup_pebs_adaptive_sample_data()
1951 data->weight.var3_w = 0; in setup_pebs_adaptive_sample_data()
1956 * But PERF_SAMPLE_TRANSACTION needs gprs->ax. in setup_pebs_adaptive_sample_data()
1968 if (event->attr.precise_ip < 2) { in setup_pebs_adaptive_sample_data()
1969 set_linear_ip(regs, gprs->ip); in setup_pebs_adaptive_sample_data()
1970 regs->flags &= ~PERF_EFLAGS_EXACT; in setup_pebs_adaptive_sample_data()
1979 u64 weight = meminfo->latency; in setup_pebs_adaptive_sample_data()
1982 data->weight.var2_w = weight & PEBS_LATENCY_MASK; in setup_pebs_adaptive_sample_data()
1992 data->weight.full = weight ?: in setup_pebs_adaptive_sample_data()
1993 intel_get_tsx_weight(meminfo->tsx_tuning); in setup_pebs_adaptive_sample_data()
1995 data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?: in setup_pebs_adaptive_sample_data()
1996 intel_get_tsx_weight(meminfo->tsx_tuning); in setup_pebs_adaptive_sample_data()
1998 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; in setup_pebs_adaptive_sample_data()
2002 data->data_src.val = get_data_src(event, meminfo->aux); in setup_pebs_adaptive_sample_data()
2003 data->sample_flags |= PERF_SAMPLE_DATA_SRC; in setup_pebs_adaptive_sample_data()
2007 data->addr = meminfo->address; in setup_pebs_adaptive_sample_data()
2008 data->sample_flags |= PERF_SAMPLE_ADDR; in setup_pebs_adaptive_sample_data()
2012 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning, in setup_pebs_adaptive_sample_data()
2013 gprs ? gprs->ax : 0); in setup_pebs_adaptive_sample_data()
2014 data->sample_flags |= PERF_SAMPLE_TRANSACTION; in setup_pebs_adaptive_sample_data()
2022 perf_regs->xmm_regs = xmm->xmm; in setup_pebs_adaptive_sample_data()
2040 (u64)(next_record - __pebs), in setup_pebs_adaptive_sample_data()
2041 basic->format_size); in setup_pebs_adaptive_sample_data()
2052 * fmt0 does not have a status bitfield (does not use in get_next_pebs_record_by_bit()
2061 for (at = base; at < top; at += cpuc->pebs_record_size) { in get_next_pebs_record_by_bit()
2072 /* clear non-PEBS bit and re-check */ in get_next_pebs_record_by_bit()
2073 pebs_status = status & cpuc->pebs_enabled; in get_next_pebs_record_by_bit()
2084 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); in intel_pmu_auto_reload_read()
2086 perf_pmu_disable(event->pmu); in intel_pmu_auto_reload_read()
2088 perf_pmu_enable(event->pmu); in intel_pmu_auto_reload_read()
2092 * Special variant of intel_pmu_save_and_restart() for auto-reload.
2097 struct hw_perf_event *hwc = &event->hw; in intel_pmu_save_and_restart_reload()
2098 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
2099 u64 period = hwc->sample_period; in intel_pmu_save_and_restart_reload()
2110 prev_raw_count = local64_read(&hwc->prev_count); in intel_pmu_save_and_restart_reload()
2111 rdpmcl(hwc->event_base_rdpmc, new_raw_count); in intel_pmu_save_and_restart_reload()
2112 local64_set(&hwc->prev_count, new_raw_count); in intel_pmu_save_and_restart_reload()
2118 * [-period, 0] in intel_pmu_save_and_restart_reload()
2122 * A) value2 - value1; in intel_pmu_save_and_restart_reload()
2125 * B) (0 - value1) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
2128 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
2139 * value2 - value1 + n * period in intel_pmu_save_and_restart_reload()
2143 local64_add(new - old + count * period, &event->count); in intel_pmu_save_and_restart_reload()
2145 local64_set(&hwc->period_left, -new); in intel_pmu_save_and_restart_reload()
2165 struct hw_perf_event *hwc = &event->hw; in __intel_pmu_pebs_event()
2171 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in __intel_pmu_pebs_event()
2173 * Now, auto-reload is only enabled in fixed period mode. in __intel_pmu_pebs_event()
2174 * The reload value is always hwc->sample_period. in __intel_pmu_pebs_event()
2175 * May need to change it, if auto-reload is enabled in in __intel_pmu_pebs_event()
2188 at += cpuc->pebs_record_size; in __intel_pmu_pebs_event()
2190 count--; in __intel_pmu_pebs_event()
2196 * The PEBS records may be drained in the non-overflow context, in __intel_pmu_pebs_event()
2215 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_core()
2216 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ in intel_pmu_drain_pebs_core()
2223 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
2224 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_core()
2229 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
2231 if (!test_bit(0, cpuc->active_mask)) in intel_pmu_drain_pebs_core()
2236 if (!event->attr.precise_ip) in intel_pmu_drain_pebs_core()
2239 n = top - at; in intel_pmu_drain_pebs_core()
2241 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_drain_pebs_core()
2257 * for auto-reload event in pmu::read(). There are no in intel_pmu_pebs_event_update_no_drain()
2260 * update the event->count for this case. in intel_pmu_pebs_event_update_no_drain()
2262 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) { in intel_pmu_pebs_event_update_no_drain()
2263 event = cpuc->events[bit]; in intel_pmu_pebs_event_update_no_drain()
2264 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_pebs_event_update_no_drain()
2272 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_nhm()
2284 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
2285 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_nhm()
2287 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
2305 pebs_status = p->status & cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
2324 if (!pebs_status && cpuc->pebs_enabled && in intel_pmu_drain_pebs_nhm()
2325 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) in intel_pmu_drain_pebs_nhm()
2326 pebs_status = p->status = cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
2339 * If these events include one PEBS and multiple non-PEBS in intel_pmu_drain_pebs_nhm()
2362 event = cpuc->events[bit]; in intel_pmu_drain_pebs_nhm()
2366 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_nhm()
2389 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_icl()
2398 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_icl()
2399 top = (struct pebs_basic *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_icl()
2401 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_icl()
2403 mask = hybrid(cpuc->pmu, pebs_events_mask) | in intel_pmu_drain_pebs_icl()
2404 (hybrid(cpuc->pmu, fixed_cntr_mask64) << INTEL_PMC_IDX_FIXED); in intel_pmu_drain_pebs_icl()
2411 for (at = base; at < top; at += cpuc->pebs_record_size) { in intel_pmu_drain_pebs_icl()
2414 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled; in intel_pmu_drain_pebs_icl()
2425 event = cpuc->events[bit]; in intel_pmu_drain_pebs_icl()
2429 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_icl()
2457 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; in intel_ds_init()
2511 pebs_qual = "-baseline"; in intel_ds_init()
2512 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; in intel_ds_init()
2526 pr_cont("PEBS-via-PT, "); in intel_ds_init()
2527 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; in intel_ds_init()