x86/crypto/sha1_ssse3_asm.S

63 #define WK(t)	(((t) & 15) * 4)(%rsp)
115 	mov	 4(HASH_PTR), B
118 	mov	16(HASH_PTR), E
126 .align 4
128 	RR F1,A,B,C,D,E,0
129 	RR F1,D,E,A,B,C,2
130 	RR F1,B,C,D,E,A,4
131 	RR F1,E,A,B,C,D,6
132 	RR F1,C,D,E,A,B,8
134 	RR F1,A,B,C,D,E,10
135 	RR F1,D,E,A,B,C,12
136 	RR F1,B,C,D,E,A,14
137 	RR F1,E,A,B,C,D,16
138 	RR F1,C,D,E,A,B,18
140 	RR F2,A,B,C,D,E,20
141 	RR F2,D,E,A,B,C,22
142 	RR F2,B,C,D,E,A,24
143 	RR F2,E,A,B,C,D,26
144 	RR F2,C,D,E,A,B,28
146 	RR F2,A,B,C,D,E,30
147 	RR F2,D,E,A,B,C,32
148 	RR F2,B,C,D,E,A,34
149 	RR F2,E,A,B,C,D,36
150 	RR F2,C,D,E,A,B,38
152 	RR F3,A,B,C,D,E,40
153 	RR F3,D,E,A,B,C,42
154 	RR F3,B,C,D,E,A,44
155 	RR F3,E,A,B,C,D,46
156 	RR F3,C,D,E,A,B,48
158 	RR F3,A,B,C,D,E,50
159 	RR F3,D,E,A,B,C,52
160 	RR F3,B,C,D,E,A,54
161 	RR F3,E,A,B,C,D,56
162 	RR F3,C,D,E,A,B,58
168 	RR F4,A,B,C,D,E,60
169 	RR F4,D,E,A,B,C,62
170 	RR F4,B,C,D,E,A,64
171 	RR F4,E,A,B,C,D,66
172 	RR F4,C,D,E,A,B,68
174 	RR F4,A,B,C,D,E,70
175 	RR F4,D,E,A,B,C,72
176 	RR F4,B,C,D,E,A,74
177 	RR F4,E,A,B,C,D,76
178 	RR F4,C,D,E,A,B,78
181 	UPDATE_HASH  4(HASH_PTR), B
184 	UPDATE_HASH 16(HASH_PTR), E
196   .set E, REG_E  define
206 	mov	E, REG_E
251  *   t1 = F(b, c, d);   e += w(i)
252  *   e += t1;           b <<= 30;   d  += w(i+1);
255  *   e += a;
256  *   t1 = e;            a >>= 7;
260 .macro RR  F, a, b, c, d, e, round
261 	add	WK(\round), \e
265 	add	T1, \e
271 	add	\a, \e
275 	mov	\e, T1
276 	SWAP_REG_NAMES \e, T1
282 	# rotate: \a<=\d, \b<=\e, \c<=\a, \d<=\b, \e<=\c
350 	movdqu	(i*4)(BUFFER_PTR), W_TMP1
372   # blended scheduling of vector and scalar instruction streams, one 4-wide
373   # vector iteration / 4 scalar rounds
378 	psrldq	$4, W_TMP1		# w[i-3]
488 	vmovdqu	(i*4)(BUFFER_PTR), W_TMP1
502 	vpsrldq	$4, W_minus_04, W_TMP1		# w[i-3]