Lines Matching +full:5 +full:d
16 __asm__ ("addcc %4,%5,%1\n\t" \
30 __asm__ ("subcc %4,%5,%1\n\t" \
51 "sllx %4,32,%5\n\t" \
53 "sub %1,%5,%5\n\t" \
54 "srlx %5,32,%5\n\t" \
55 "addcc %4,%5,%4\n\t" \
56 "srlx %7,32,%5\n\t" \
57 "mulx %3,%5,%3\n\t" \
58 "mulx %2,%5,%5\n\t" \
64 "addcc %5,%4,%5\n\t" \
67 "add %5,%2,%0" \
76 #define udiv_qrnnd(q, r, n1, n0, d) \ argument
79 __d1 = (d >> 32); \
80 __d0 = (USItype)d; \
88 __q1--, __r1 += (d); \
89 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
91 __q1--, __r1 += (d); \
101 __q0--, __r0 += (d); \
102 if (__r0 >= (d)) \
104 __q0--, __r0 += (d); \