Lines Matching +full:0 +full:x4b
55 /* When an irrecoverable trap occurs at tl > 0, the trap entry
74 printk(KERN_EMERG "TRAPLOG: Error at trap level 0x%lx, " in dump_tl1_traplog()
78 for (i = 0; i < limit; i++) { in dump_tl1_traplog()
94 0, lvl, SIGTRAP) == NOTIFY_STOP) in bad_trap()
97 if (lvl < 0x100) { in bad_trap()
102 lvl -= 0x100; in bad_trap()
108 regs->tpc &= 0xffffffff; in bad_trap()
109 regs->tnpc &= 0xffffffff; in bad_trap()
120 0, lvl, SIGTRAP) == NOTIFY_STOP) in bad_trap_tl1()
125 sprintf (buffer, "Bad trap %lx at tl>0", lvl); in bad_trap_tl1()
153 ret = 0; in sprintf_dimm()
164 int ret = 0; in register_dimm_printer()
193 0, 0x8, SIGTRAP) == NOTIFY_STOP) in spitfire_insn_access_exception()
202 regs->tpc &= 0xffffffff; in spitfire_insn_access_exception()
203 regs->tnpc &= 0xffffffff; in spitfire_insn_access_exception()
213 0, 0x8, SIGTRAP) == NOTIFY_STOP) in spitfire_insn_access_exception_tl1()
223 unsigned short ctx = (type_ctx & 0xffff); in sun4v_insn_access_exception()
226 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_insn_access_exception()
237 regs->tpc &= 0xffffffff; in sun4v_insn_access_exception()
238 regs->tnpc &= 0xffffffff; in sun4v_insn_access_exception()
246 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_insn_access_exception_tl1()
273 if ((insn & 0xc0800000) == 0xc0800000) { /* op=3, op3[4]=1 */ in is_no_fault_exception()
274 if (insn & 0x2000) /* immediate offset */ in is_no_fault_exception()
278 if ((asi & 0xf6) == ASI_PNF) { in is_no_fault_exception()
279 if (insn & 0x200000) /* op3[2], stores */ in is_no_fault_exception()
281 if (insn & 0x1000000) /* op3[5:4]=3 (fp) */ in is_no_fault_exception()
296 0, 0x30, SIGTRAP) == NOTIFY_STOP) in spitfire_data_access_exception()
332 0, 0x30, SIGTRAP) == NOTIFY_STOP) in spitfire_data_access_exception_tl1()
342 unsigned short ctx = (type_ctx & 0xffff); in sun4v_data_access_exception()
345 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_data_access_exception()
371 regs->tpc &= 0xffffffff; in sun4v_data_access_exception()
372 regs->tnpc &= 0xffffffff; in sun4v_data_access_exception()
377 /* MCD (Memory Corruption Detection) disabled trap (TT=0x19) in HV in sun4v_data_access_exception()
402 0, 0x8, SIGTRAP) == NOTIFY_STOP) in sun4v_data_access_exception_tl1()
422 for (va = 0; va < (PAGE_SIZE << 1); va += 32) { in spitfire_clean_and_reenable_l1_caches()
423 spitfire_put_icache_tag(va, 0x0); in spitfire_clean_and_reenable_l1_caches()
424 spitfire_put_dcache_tag(va, 0x0); in spitfire_clean_and_reenable_l1_caches()
430 "stxa %0, [%%g0] %1\n\t" in spitfire_clean_and_reenable_l1_caches()
441 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in spitfire_enable_estate_errors()
449 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
450 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
451 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
452 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
453 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
454 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
455 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
456 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
457 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
458 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
459 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
460 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
461 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
462 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
463 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
464 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
465 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
466 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
467 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
468 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
469 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
470 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
471 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
472 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
473 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
474 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
475 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
476 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
477 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
478 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
479 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
480 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
491 scode = ecc_syndrome_table[udbl & 0xff]; in spitfire_log_udb_syndrome()
492 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0) in spitfire_log_udb_syndrome()
502 scode = ecc_syndrome_table[udbh & 0xff]; in spitfire_log_udb_syndrome()
503 if (sprintf_dimm(scode, afar, memmod_str, sizeof(memmod_str)) < 0) in spitfire_log_udb_syndrome()
527 0, TRAP_TYPE_CEE, SIGTRAP); in spitfire_cee_log()
551 0, tt, SIGTRAP); in spitfire_ue_log()
568 regs->tpc &= 0xffffffff; in spitfire_ue_log()
569 regs->tnpc &= 0xffffffff; in spitfire_ue_log()
571 force_sig_fault(SIGBUS, BUS_OBJERR, (void *)0); in spitfire_ue_log()
581 tl1 = (status_encoded & SFSTAT_TL_GT_ONE) ? 1 : 0; in spitfire_access_error()
607 "stxa %0, [%1] %2\n\t" in spitfire_access_error()
611 "r" (0x0), "i" (ASI_UDB_ERROR_W)); in spitfire_access_error()
615 "stxa %0, [%1] %2\n\t" in spitfire_access_error()
619 "r" (0x18), "i" (ASI_UDB_ERROR_W)); in spitfire_access_error()
636 __asm__ __volatile__("ldxa [%%g0] %1, %0" in cheetah_enable_pcache()
640 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_enable_pcache()
719 { 0, NULL },
760 { 0, NULL },
819 { 0, NULL },
835 if ((afsr & CHAFSR_TL1) != 0UL) in cheetah_get_error_log()
862 largest_size = 0UL; in cheetah_ecache_flush_init()
863 smallest_linesize = ~0UL; in cheetah_ecache_flush_init()
865 for (i = 0; i < NR_CPUS; i++) { in cheetah_ecache_flush_init()
881 if (largest_size == 0UL || smallest_linesize == ~0UL) { in cheetah_ecache_flush_init()
892 if (ecache_flush_physbase == ~0UL) { in cheetah_ecache_flush_init()
901 for (order = 0; order < NR_PAGE_ORDERS; order++) { in cheetah_ecache_flush_init()
912 memset(cheetah_error_log, 0, PAGE_SIZE << order); in cheetah_ecache_flush_init()
917 for (i = 0; i < 2 * NR_CPUS; i++) in cheetah_ecache_flush_init()
920 __asm__ ("rdpr %%ver, %0" : "=r" (ver)); in cheetah_ecache_flush_init()
923 cheetah_error_table = &__jalapeno_error_table[0]; in cheetah_ecache_flush_init()
925 } else if ((ver >> 32) == 0x003e0015) { in cheetah_ecache_flush_init()
926 cheetah_error_table = &__cheetah_plus_error_table[0]; in cheetah_ecache_flush_init()
929 cheetah_error_table = &__cheetah_error_table[0]; in cheetah_ecache_flush_init()
957 __asm__ __volatile__("1: subcc %0, %4, %0\n\t" in cheetah_flush_ecache()
959 " ldxa [%2 + %0] %3, %%g0\n\t" in cheetah_flush_ecache()
961 : "0" (flush_size), "r" (flush_base), in cheetah_flush_ecache()
973 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t" in cheetah_flush_ecache_line()
995 for (addr = 0; addr < icache_size; addr += icache_line_size) { in __cheetah_flush_icache()
996 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" in __cheetah_flush_icache()
1009 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_flush_icache()
1010 "or %0, %2, %%g1\n\t" in cheetah_flush_icache()
1020 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_flush_icache()
1034 for (addr = 0; addr < dcache_size; addr += dcache_line_size) { in cheetah_flush_dcache()
1035 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" in cheetah_flush_dcache()
1055 for (addr = 0; addr < dcache_size; addr += dcache_line_size) { in cheetah_plus_zap_dcache_parity()
1060 "stxa %0, [%1] %2\n\t" in cheetah_plus_zap_dcache_parity()
1067 "stxa %%g0, [%0] %1\n\t" in cheetah_plus_zap_dcache_parity()
1104 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
1111 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
1112 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
1113 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
1114 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
1115 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
1116 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
1148 unsigned long tmp = 0; in cheetah_get_hipri()
1151 for (i = 0; cheetah_error_table[i].mask; i++) { in cheetah_get_hipri()
1152 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL) in cheetah_get_hipri()
1162 for (i = 0; cheetah_error_table[i].mask; i++) { in cheetah_get_string()
1163 if ((bit & cheetah_error_table[i].mask) != 0UL) in cheetah_get_string()
1178 (afsr & CHAFSR_TL1) ? 1 : 0); in cheetah_log_errors()
1237 info->dcache_data[0], in cheetah_log_errors()
1252 info->icache_data[0], in cheetah_log_errors()
1267 info->ecache_data[0], in cheetah_log_errors()
1273 while (afsr != 0UL) { in cheetah_log_errors()
1290 int ret = 0; in cheetah_recheck_errors()
1292 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_recheck_errors()
1295 if ((afsr & cheetah_afsr_errors) != 0) { in cheetah_recheck_errors()
1297 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t" in cheetah_recheck_errors()
1305 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_recheck_errors()
1348 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_fecc_handler()
1350 "stxa %%g1, [%%g0] %0\n\t" in cheetah_fecc_handler()
1358 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_fecc_handler()
1360 "stxa %%g1, [%%g0] %0\n\t" in cheetah_fecc_handler()
1372 recoverable = 0; in cheetah_fecc_handler()
1385 recoverable = 0; in cheetah_fecc_handler()
1409 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t" in cheetah_fix_ce()
1410 "andn %0, %1, %%g1\n\t" in cheetah_fix_ce()
1429 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t" in cheetah_fix_ce()
1432 "ldxa [%0] %3, %%g0\n\t" in cheetah_fix_ce()
1442 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t" in cheetah_fix_ce()
1451 ret = 0; in cheetah_fix_ce()
1455 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t" in cheetah_fix_ce()
1468 return 0; in cheetah_check_main_memory()
1504 if (is_memory && (afsr & CHAFSR_CE) != 0UL) { in cheetah_cee_handler()
1514 flush_all = flush_line = 0; in cheetah_cee_handler()
1515 if ((afsr & CHAFSR_EDC) != 0UL) { in cheetah_cee_handler()
1520 } else if ((afsr & CHAFSR_CPC) != 0UL) { in cheetah_cee_handler()
1531 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_cee_handler()
1533 "stxa %%g1, [%%g0] %0\n\t" in cheetah_cee_handler()
1547 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_cee_handler()
1549 "stxa %%g1, [%%g0] %0\n\t" in cheetah_cee_handler()
1561 recoverable = 0; in cheetah_cee_handler()
1585 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1587 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1595 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1597 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1642 flush_all = flush_line = 0; in cheetah_deferred_handler()
1643 if ((afsr & CHAFSR_EDU) != 0UL) { in cheetah_deferred_handler()
1648 } else if ((afsr & CHAFSR_BERR) != 0UL) { in cheetah_deferred_handler()
1659 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1661 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1675 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_deferred_handler()
1677 "stxa %%g1, [%%g0] %0\n\t" in cheetah_deferred_handler()
1689 recoverable = 0; in cheetah_deferred_handler()
1702 recoverable = 0; in cheetah_deferred_handler()
1721 if ((regs->tstate & TSTATE_PRIV) == 0UL) { in cheetah_deferred_handler()
1734 recoverable = 0; in cheetah_deferred_handler()
1741 recoverable = 0; in cheetah_deferred_handler()
1753 recoverable = 0; in cheetah_deferred_handler()
1762 * Bit0: 0=dcache,1=icache
1763 * Bit1: 0=recoverable,1=unrecoverable
1770 if (type & 0x1) in cheetah_plus_parity_error()
1777 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t" in cheetah_plus_parity_error()
1779 "stxa %%g1, [%%g0] %0\n\t" in cheetah_plus_parity_error()
1786 if (type & 0x2) { in cheetah_plus_parity_error()
1789 (type & 0x1) ? 'I' : 'D', in cheetah_plus_parity_error()
1797 (type & 0x1) ? 'I' : 'D', in cheetah_plus_parity_error()
1804 /*0x00*/u64 err_handle;
1807 /*0x08*/u64 err_stick;
1809 /*0x10*/u8 reserved_1[3];
1812 /*0x13*/u8 err_type;
1813 #define SUN4V_ERR_TYPE_UNDEFINED 0
1823 /*0x14*/u32 err_attrs;
1824 #define SUN4V_ERR_ATTRS_PROCESSOR 0x00000001
1825 #define SUN4V_ERR_ATTRS_MEMORY 0x00000002
1826 #define SUN4V_ERR_ATTRS_PIO 0x00000004
1827 #define SUN4V_ERR_ATTRS_INT_REGISTERS 0x00000008
1828 #define SUN4V_ERR_ATTRS_FPU_REGISTERS 0x00000010
1829 #define SUN4V_ERR_ATTRS_SHUTDOWN_RQST 0x00000020
1830 #define SUN4V_ERR_ATTRS_ASR 0x00000040
1831 #define SUN4V_ERR_ATTRS_ASI 0x00000080
1832 #define SUN4V_ERR_ATTRS_PRIV_REG 0x00000100
1833 #define SUN4V_ERR_ATTRS_SPSTATE_MSK 0x00000600
1834 #define SUN4V_ERR_ATTRS_MCD 0x00000800
1836 #define SUN4V_ERR_ATTRS_MODE_MSK 0x03000000
1838 #define SUN4V_ERR_ATTRS_RES_QUEUE_FULL 0x80000000
1840 #define SUN4V_ERR_SPSTATE_FAULTED 0
1848 /*0x18*/u64 err_raddr;
1851 /*0x20*/u32 err_size;
1854 /*0x24*/u16 err_cpu;
1857 /*0x26*/u16 err_secs;
1860 /*0x28*/u8 err_asi;
1862 /*0x29*/u8 reserved_2;
1865 /*0x2a*/u16 err_asr;
1866 #define SUN4V_ERR_ASR_VALID 0x8000
1868 /*0x2c*/u32 reserved_3;
1869 /*0x30*/u64 reserved_4;
1870 /*0x38*/u64 reserved_5;
1873 static atomic_t sun4v_resum_oflow_cnt = ATOMIC_INIT(0);
1874 static atomic_t sun4v_nonresum_oflow_cnt = ATOMIC_INIT(0);
1922 for (i = 0; i < ARRAY_SIZE(attr_names); i++) { in sun4v_emit_err_attr_strings()
1959 addr = compute_effective_address(regs, insn, 0); in sun4v_report_real_raddr()
1961 printk("%s: insn effective address [0x%016llx]\n", in sun4v_report_real_raddr()
1973 printk("%s: TPC [0x%016lx] <%pS>\n", in sun4v_log_error()
1977 pfx, raw_ptr[0], raw_ptr[1], raw_ptr[2], raw_ptr[3]); in sun4v_log_error()
1981 printk("%s: handle [0x%016llx] stick [0x%016llx]\n", in sun4v_log_error()
1987 printk("%s: attrs [0x%08x] < ", pfx, attrs); in sun4v_log_error()
1997 printk("%s: raddr [0x%016llx]\n", pfx, ent->err_raddr); in sun4v_log_error()
1999 if (ent->err_raddr == ~(u64)0) in sun4v_log_error()
2004 printk("%s: size [0x%x]\n", pfx, ent->err_size); in sun4v_log_error()
2013 printk("%s: asi [0x%02x]\n", pfx, ent->err_asi); in sun4v_log_error()
2018 (ent->err_asr & SUN4V_ERR_ASR_VALID) != 0) in sun4v_log_error()
2019 printk("%s: reg [0x%04x]\n", in sun4v_log_error()
2024 if ((cnt = atomic_read(ocnt)) != 0) { in sun4v_log_error()
2025 atomic_set(ocnt, 0); in sun4v_log_error()
2037 if (notify_die(DIE_TRAP, "MCD error", regs, 0, 0x34, in do_mcd_err()
2095 ent->err_handle = 0; in sun4v_resum_error()
2145 (insn >> 25) & 0x1f); in sun4v_get_vaddr()
2147 return 0; in sun4v_get_vaddr()
2161 if (addr == ~(u64)0) { in sun4v_nonresum_error_user_handled()
2174 while (page_cnt-- > 0) { in sun4v_nonresum_error_user_handled()
2213 ent->err_handle = 0; in sun4v_nonresum_error()
2322 unsigned long fsr = current_thread_info()->xfsr[0]; in do_fpe_common()
2326 regs->tpc &= 0xffffffff; in do_fpe_common()
2327 regs->tnpc &= 0xffffffff; in do_fpe_common()
2330 if ((fsr & 0x1c000) == (1 << 14)) { in do_fpe_common()
2331 if (fsr & 0x10) in do_fpe_common()
2333 else if (fsr & 0x08) in do_fpe_common()
2335 else if (fsr & 0x04) in do_fpe_common()
2337 else if (fsr & 0x02) in do_fpe_common()
2339 else if (fsr & 0x01) in do_fpe_common()
2351 0, 0x24, SIGFPE) == NOTIFY_STOP) in do_fpieee()
2363 int ret = 0; in do_fpother()
2366 0, 0x25, SIGFPE) == NOTIFY_STOP) in do_fpother()
2369 switch ((current_thread_info()->xfsr[0] & 0x1c000)) { in do_fpother()
2387 0, 0x26, SIGEMT) == NOTIFY_STOP) in do_tof()
2393 regs->tpc &= 0xffffffff; in do_tof()
2394 regs->tnpc &= 0xffffffff; in do_tof()
2406 0, 0x28, SIGFPE) == NOTIFY_STOP) in do_div0()
2412 regs->tpc &= 0xffffffff; in do_div0()
2413 regs->tnpc &= 0xffffffff; in do_div0()
2445 for (i = 0; i < 9; i++) in user_instruction_dump()
2454 int count = 0; in show_stack()
2456 int graph = 0; in show_stack()
2463 if (ksp == 0UL) { in show_stack()
2465 asm("mov %%fp, %0" : "=r" (ksp)); in show_stack()
2523 int count = 0; in die_if_kernel()
2533 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV); in die_if_kernel()
2556 regs->tpc &= 0xffffffff; in die_if_kernel()
2557 regs->tnpc &= 0xffffffff; in die_if_kernel()
2567 #define VIS_OPCODE_MASK ((0x3 << 30) | (0x3f << 19))
2568 #define VIS_OPCODE_VAL ((0x2 << 30) | (0x36 << 19))
2578 0, 0x10, SIGILL) == NOTIFY_STOP) in do_illegal_instruction()
2586 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ { in do_illegal_instruction()
2589 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ { in do_illegal_instruction()
2619 0, 0x34, SIGSEGV) == NOTIFY_STOP) in mem_address_unaligned()
2637 0, 0x34, SIGSEGV) == NOTIFY_STOP) in sun4v_do_mna()
2661 0, 0x8, SIGSEGV) == NOTIFY_STOP) in sun4v_mem_corrupt_detect_precise()
2691 regs->tpc &= 0xffffffff; in sun4v_mem_corrupt_detect_precise()
2692 regs->tnpc &= 0xffffffff; in sun4v_mem_corrupt_detect_precise()
2702 0, 0x11, SIGILL) == NOTIFY_STOP) in do_privop()
2706 regs->tpc &= 0xffffffff; in do_privop()
2707 regs->tnpc &= 0xffffffff; in do_privop()
2814 regs->tpc &= 0xffffffff; in do_getpsr()
2815 regs->tnpc &= 0xffffffff; in do_getpsr()
2819 u64 cpu_mondo_counter[NR_CPUS] = {0};
2832 p->pgd_paddr = 0; in init_cur_cpu_trap()