Lines Matching +full:clear +full:- +full:bit

1 /* SPDX-License-Identifier: GPL-2.0 */
6 	 * We pass the AFAR in as-is, and we encode the status
7 	 * information as described in asm-sparc64/sfafsr.h
40 	 * error bits as-needed.  We only clear them if the UE bit is
42 	 * if the CE bit is set.
44 	 * NOTE: UltraSparc-I/II have high and low UDB error
46 	 *       present on those chips.  UltraSparc-IIi only
74 1:	/* Ok, now that we've latched the error state, clear the
105 	.size		__spitfire_access_error,.-__spitfire_access_error
112 	 * 1) single-bit ECC errors during UDB reads to system
114 	 * 2) data parity errors during write-back events
118 	 * the front-end of the processor.
122 	 * For trap level >1 we just clear the CE bit in the AFSR and
155 	.size		__spitfire_cee_trap,.-__spitfire_cee_trap
165 	stxa		%g0, [%g3] ASI_DMMU	! Clear SFSR.FaultValid bit
183 	.size		__spitfire_data_access_exception_tl1,.-__spitfire_data_access_exception_tl1
193 	stxa		%g0, [%g3] ASI_DMMU	! Clear SFSR.FaultValid bit
203 	.size		__spitfire_data_access_exception,.-__spitfire_data_access_exception
212 	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit
222 	.size		__spitfire_insn_access_exception_tl1,.-__spitfire_insn_access_exception_tl1
231 	stxa		%g0, [%g3] ASI_IMMU	! Clear FaultValid bit
241 	.size		__spitfire_insn_access_exception,.-__spitfire_insn_access_exception