58 	upa_writeq(~(u64)0, iommu->iommu_flushinv);  in pci_fire_pbm_iommu_init()
65 	upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase);  in pci_fire_pbm_iommu_init()
72 	upa_writeq(control, iommu->iommu_control);  in pci_fire_pbm_iommu_init()
180 	upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi_num));  in pci_fire_dequeue_msi()
196 	upa_writeq(head, pbm->pbm_regs + EVENT_QUEUE_HEAD(msiqid));  in pci_fire_set_head()
208 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
210 	upa_writeq(MSI_CLEAR_EQWR_N, pbm->pbm_regs + MSI_CLEAR(msi));  in pci_fire_msi_setup()
214 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_setup()
227 	upa_writeq(val, pbm->pbm_regs + MSI_MAP(msi));  in pci_fire_msi_teardown()
246 	upa_writeq((EVENT_QUEUE_BASE_ADDR_ALL_ONES |  in pci_fire_msiq_alloc()
250 	upa_writeq(pbm->portid << 6, pbm->pbm_regs + IMONDO_DATA0);  in pci_fire_msiq_alloc()
251 	upa_writeq(0, pbm->pbm_regs + IMONDO_DATA1);  in pci_fire_msiq_alloc()
253 	upa_writeq(pbm->msi32_start, pbm->pbm_regs + MSI_32BIT_ADDR);  in pci_fire_msiq_alloc()
254 	upa_writeq(pbm->msi64_start, pbm->pbm_regs + MSI_64BIT_ADDR);  in pci_fire_msiq_alloc()
257 		upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_HEAD(i));  in pci_fire_msiq_alloc()
258 		upa_writeq(0, pbm->pbm_regs + EVENT_QUEUE_TAIL(i));  in pci_fire_msiq_alloc()
294 	upa_writeq(val, imap_reg);  in pci_fire_msiq_build_irq()
302 	upa_writeq(EVENT_QUEUE_CONTROL_SET_EN,  in pci_fire_msiq_build_irq()
371 	upa_writeq(FIRE_PARITY_ENAB,  in pci_fire_hw_init()
374 	upa_writeq((FIRE_FATAL_RESET_SPARE |  in pci_fire_hw_init()
384 	upa_writeq(~(u64)0, pbm->controller_regs + FIRE_CORE_INTR_ENABLE);  in pci_fire_hw_init()
390 	upa_writeq(val, pbm->pbm_regs + FIRE_TLU_CTRL);  in pci_fire_hw_init()
391 	upa_writeq(0, pbm->pbm_regs + FIRE_TLU_DEV_CTRL);  in pci_fire_hw_init()
392 	upa_writeq(FIRE_TLU_LINK_CTRL_CLK,  in pci_fire_hw_init()
395 	upa_writeq(0, pbm->pbm_regs + FIRE_LPU_RESET);  in pci_fire_hw_init()
396 	upa_writeq(FIRE_LPU_LLCFG_VC0, pbm->pbm_regs + FIRE_LPU_LLCFG);  in pci_fire_hw_init()
397 	upa_writeq((FIRE_LPU_FCTRL_UCTRL_N | FIRE_LPU_FCTRL_UCTRL_P),  in pci_fire_hw_init()
399 	upa_writeq(((0xffff << 16) | (0x0000 << 0)),  in pci_fire_hw_init()
401 	upa_writeq(3000000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG2);  in pci_fire_hw_init()
402 	upa_writeq(500000, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG3);  in pci_fire_hw_init()
403 	upa_writeq((2 << 16) | (140 << 8),  in pci_fire_hw_init()
405 	upa_writeq(0, pbm->pbm_regs + FIRE_LPU_LTSSM_CFG5);  in pci_fire_hw_init()
407 	upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_DMC_IENAB);  in pci_fire_hw_init()
408 	upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_A);  in pci_fire_hw_init()
409 	upa_writeq(0, pbm->pbm_regs + FIRE_DMC_DBG_SEL_B);  in pci_fire_hw_init()
411 	upa_writeq(~(u64)0, pbm->pbm_regs + FIRE_PEC_IENAB);  in pci_fire_hw_init()