sparc/kernel/irq_32.c

1 // SPDX-License-Identifier: GPL-2.0
12  *  Copyright (C) 1998-2000 Anton Blanchard (anton@samba.org)
98  * 32-bit values in that case.  Since this is similar to sparc64,
106  * We keep a map of per-PIL enable interrupts.  These get wired
107  * up via the irq_chip->startup() method which gets invoked by
168 	pil = p->pil;  in irq_link()
170 	p->next = irq_map[pil];  in irq_link()
186 	BUG_ON(p->pil >= SUN4D_MAX_IRQ);  in irq_unlink()
187 	pnext = &irq_map[p->pil];  in irq_unlink()
189 		pnext = &(*pnext)->next;  in irq_unlink()
190 	*pnext = p->next;  in irq_unlink()
214 	seq_printf(p, "     Non-maskable interrupts\n");  in arch_show_interrupts()
229 		struct irq_bucket *next = p->next;  in handler_irq()
231 		generic_handle_irq(p->irq);  in handler_irq()
249 		return -1;  in sparc_floppy_request_irq()
254 	cpu_irq = (irq & (NR_IRQS - 1));  in sparc_floppy_request_irq()
258 	table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_one = SPARC_RD_PSR_L0; \  in sparc_floppy_request_irq()
259 	table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two = \  in sparc_floppy_request_irq()
261 			     (unsigned long) &table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_two);\  in sparc_floppy_request_irq()
262 	table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_three = SPARC_RD_WIM_L3; \  in sparc_floppy_request_irq()
263 	table[SP_TRAP_IRQ1+(cpu_irq-1)].inst_four = SPARC_NOP;  in sparc_floppy_request_irq()
281 	 * XXX Correct thing whould be to flush only I- and D-cache lines  in sparc_floppy_request_irq()
283 	 * writing we have no CPU-neutral interface to fine-grained flushes.  in sparc_floppy_request_irq()
334  * fit in with the idea of being able to tune your kernel for your machine