Lines Matching full:iii

142 /* SpitFire and later extended ASIs.  The "(III)" marker designates
143  * UltraSparc-III and later specific ASIs.  The "(CMT)" marker designates
168 #define ASI_PCACHE_DATA_STATUS	0x30 /* (III) PCache data stat RAM diag	*/
169 #define ASI_PCACHE_DATA		0x31 /* (III) PCache data RAM diag	*/
170 #define ASI_PCACHE_TAG		0x32 /* (III) PCache tag RAM diag	*/
171 #define ASI_PCACHE_SNOOP_TAG	0x33 /* (III) PCache snoop tag RAM diag	*/
172 #define ASI_QUAD_LDD_PHYS	0x34 /* (III+) PADDR, qword load	*/
173 #define ASI_WCACHE_VALID_BITS	0x38 /* (III) WCache Valid Bits diag	*/
174 #define ASI_WCACHE_DATA		0x39 /* (III) WCache data RAM diag	*/
175 #define ASI_WCACHE_TAG		0x3a /* (III) WCache tag RAM diag	*/
176 #define ASI_WCACHE_SNOOP_TAG	0x3b /* (III) WCache snoop tag RAM diag	*/
177 #define ASI_QUAD_LDD_PHYS_L	0x3c /* (III+) PADDR, qw-load, l-endian	*/
178 #define ASI_SRAM_FAST_INIT	0x40 /* (III+) Fast SRAM init		*/
188 #define ASI_DCACHE_INVALIDATE	0x42 /* (III) DCache Invalidate diag	*/
189 #define ASI_DCACHE_UTAG		0x43 /* (III) DCache uTag diag		*/
190 #define ASI_DCACHE_SNOOP_TAG	0x44 /* (III) DCache snoop tag RAM diag	*/
192 #define ASI_DCU_CONTROL_REG	0x45 /* (III) DCache Unit Control reg	*/
199 #define ASI_SAFARI_CONFIG	0x4a /* (III) Safari Config Register	*/
200 #define ASI_SAFARI_ADDRESS	0x4a /* (III) Safari Address Register	*/
220 #define ASI_IIU_INST_TRAP	0x60 /* (III) Instruction Breakpoint	*/
226 #define ASI_IC_STAG		0x68 /* (III) Insn cache snoop tag ram	*/
229 #define ASI_BRPRED_ARRAY	0x6f /* (III) Branch Prediction RAM diag*/
232 #define ASI_MCU_CTRL_REG	0x72 /* (III) Memory controller regs	*/
233 #define ASI_EC_DATA		0x74 /* (III) E-cache data staging reg	*/
234 #define ASI_EC_CTRL		0x75 /* (III) E-cache control reg	*/
239 #define ASI_INTR_DATAN_W	0x77 /* (III) Out irq vector data reg N	*/
240 #define ASI_INTR_DISPATCH_W	0x77 /* (III) Interrupt vector dispatch	*/
249 #define ASI_INTR_DATAN_R	0x7f /* (III) In irq vector data reg N	*/