Lines Matching +full:phase +full:- +full:locked

1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define TSB_EXTENSION_P		0x0000000000000048 /* Ultra-III and later		*/
25 #define TSB_EXTENSION_S		0x0000000000000050 /* Ultra-III and later, D-TLB only	*/
26 #define TSB_EXTENSION_N		0x0000000000000058 /* Ultra-III and later		*/
27 #define TLB_TAG_ACCESS_EXT	0x0000000000000060 /* Ultra-III+ and later		*/
38 #define SPITFIRE_HIGHEST_LOCKED_TLBENT	(64 - 1)
39 #define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)
58  * to identify the CPU type in the setup phase
201 /* Cheetah has "all non-locked" tlb flushes. */
218 /* Cheetah has a 4-tlb layout so direct access is a bit different.
220  * used only for locked and >8K sized translations.  One exists for
223  * The third TLB is for data accesses to 8K non-locked translations, is
225  * instruction accesses to 8K non-locked translations, is 2 way
230  * the problem for me. -DaveM