include/asm/hypervisor.h

1 /* SPDX-License-Identifier: GPL-2.0 */
16  * -----------------------------------------------
23  * -----------------------------------------------
25  * The second type are "hyper-fast traps" which encode the function
27  * numbers > 0x80.  The register usage for hyper-fast traps is as
30  * -----------------------------------------------
36  * -----------------------------------------------
44  * defined below.  So, for example, if a hyper-fast trap takes
49  * is invalid, HV_EBADTRAP will be returned in %o0.  Also, all 64-bits
64 #define HV_ENOINTR			3  /* Invalid interrupt id         */
91  * state.  The 64-bit exit code may be passed to a service entity as
99  *       the guest code.  A non-zero exit code denotes a guest specific
175  * implementated granularity is given by the 'watchdog-resolution'
178  * 'watchdog-max-timeout' property of the 'platform' node.
185  * If the 'timeout' value exceeds the value of the 'max-watchdog-timeout'
190  * return status is EOK or EINVAL.  A non-zero return value indicates the
192  * If less than one millisecond remains, the return value is '1'.  If the
205  * re-enabled upon returning to normal execution.  The API has been designed
207  * be used directly as the timeout argument of the re-enable call.
225  * A CPU ID is a pre-assigned 16-bit value that uniquely identifies a
228  * array in real memory, of which each 16-bit word is a CPU ID.  CPU
230  * the number of entries (16-bit words) in the CPU list, and the
296  * an interrupt (device, %stick_compare, or cross-call) is targeted to
314  * invoked the cpu-yield service, that vCPU will be resumed.
315  * Poke interrupts may only be sent to valid, non-local CPUs.
332  *		EINVAL		Invalid queue or number of entries is less
351  *	-----		-------------------------
355  *	0x3f		non-resumable error queue
394  * ARG0-1:	CPU list
397  * ERRORS:	EBADALIGN	Mondo data is not 64-byte aligned or CPU list
398  *				is not 2-byte aligned.
408  * Send a mondo interrupt to the CPUs in the given CPU list with the
409  * 64-bytes at the given data real address.  The data must be 64-byte
536  * The fault status block is a multiple of 64-bytes and must be aligned
537  * on a 64-byte boundary.
575 /* Values 16 --> -2 are reserved.  */
576 #define HV_FAULT_TYPE_MULTIPLE	-1
595  * Create a non-permanent mapping using the given TTE, virtual
632  *					to an 8-byte boundary, or TSB base
649  *       mmu-max-#tsbs property of the cpu's corresponding "cpu" node in the
668  * non-zero contexts.  The TSB descriptions pointer is a pointer to an
686  *		ENOTSUPPORTED		ARG0 or ARG1 is non-zero
707  *		ENOTSUPPORTED		ARG0 or ARG1 is non-zero
709  * Demaps all non-permanent virtual page mappings previously specified
727  *		ENOTSUPPORTED		ARG0 or ARG1 is non-zero
729  * Demaps all non-permanent virtual page mappings previously specified
785  * Configure the MMU fault status area for the calling CPU.  A 64-byte
809  * translation is disabled, any non-zero value will enable
924  *       error reported via a resumable or non-resumable trap.  The second
943  * length minus 1 to be fetches from main system memory.  Less than
952  * M7 and later processors provide an on-chip coprocessor which
965  * RET1:	size (in bytes) of CCB array that was accepted (might be less
978  *		ETOOMANY	too many ccbs with all-or-nothing flag
985  *					0 - exact CCB could not be executed
986  *					1 - CCB opcode cannot be executed
987  *					2 - CCB version cannot be executed
988  *					3 - vcpu cannot execute CCBs
989  *					4 - no CCBs can be executed
1023  *			- RET1[0]: CCB state
1024  *			- RET1[1]: dax unit
1025  *			- RET1[2]: queue number
1026  *			- RET1[3]: queue position
1085  * The hypervisor maintains the time of day on a per-domain basis.
1089  * Time is described by a single unsigned 64-bit word which is the
1142  * A virtual BREAK is represented by the 64-bit value -1.
1144  * A virtual HUP signal is represented by the 64-bit value -2.
1158  * invalid except for the 64-bit value -1 which is used to send a
1178  * A virtual BREAK is represented by the 64-bit RET1 value -1.
1180  * A virtual HUP signal is represented by the 64-bit RET1 value -2.
1234  * of size 32-bytes aligned on a 32-byte boundary.  It is treated as a NULL
1235  * terminated 7-bit ASCII string of up to 31 characters not including the
1342  * round-robin trap trace queue within which the hypervisor writes
1343  * 64-byte entries detailing hyperprivileged traps taken n behalf of
1347  * The trap trace control structure is 64-bytes long and placed at the
1362  * in the trap-trace buffer.  The tail offset is the offset of the
1373 	unsigned char	hpstate;	/* Hyper-privileged state	*/
1415  *		EBADALIGN	Real address not aligned on 64-byte boundary
1419  * base address of the trap trace queue and must be 64-byte aligned.
1422  * sized for a power of two number of 64-byte trap trace entries plus
1423  * an initial 64-byte control structure.
1445  * Returns the size and location of the previously declared trap-trace
1462  * "(uint64_t) -1" to enable, and "(uint64_t) 0" to disable all
1463  * tracing - which will ensure future compatibility.
1476  * state in RET1.  A guest should pass a non-zero value to freeze and
1484  * ARG0:	tag (16-bits)
1493  * is modified - none of the other registers holding arguments are
1521  *		EBADALIGN	Real address is not aligned on a 64-byte
1523  *		EINVAL		Size is non-zero but less than minimum size
1529  * provided for the domain dump buffer must be 64-byte aligned.  The
1537  *       "snapshots" of any dump-buffer information.  Each call to
1564 /* Device interrupt services.
1575  *			consistes of the lower 28-bits of the hi-cell of the
1579  *	devino		Device interrupt number.  Specifies the relative
1580  *			interrupt number within the device.  The unique
1582  *			identify a specific device interrupt.
1585  *			      "interrupts" property or "interrupt-map" property
1588  *	sysino		System interrupt number.  A 64-bit unsigned interger
1589  *			representing a unique interrupt within a virtual
1592  *	intr_state	A flag representing the interrupt state for a given
1600 #define HV_INTR_STATE_RECEIVED		1 /* Interrupt received by hardware */
1601 #define HV_INTR_STATE_DELIVERED		2 /* Interrupt delivered to queue */
1615  * Converts a device specific interrupt number of the given
1633  * Returns interrupt enabled state in RET1 for the interrupt defined
1650  * Set the 'enabled' state of the interrupt sysino.
1667  * Returns current state of the interrupt defined by the given sysino.
1683  * Sets the current state of the interrupt described by the given sysino
1687  *       interrupt for sysino.
1703  * Returns CPU that is the current target of the interrupt defined by
1722  * Set the target CPU for the interrupt defined by the given sysino.
1839  * See the terminology descriptions in the device interrupt services
1843  *	tsbnum		TSB number.  Indentifies which io-tsb is used.
1850  *	tsbid		A 64-bit aligned data structure which contains
1858  *			of the attritbute bits are stores in a 64-bit
1861  *	r_addr		64-bit real address
1865  *			A PCI device address ia a 32-bit unsigned integer
1882  *			or failed.  0 means no error, non-0 means some error
1894  *	"size based byte swap" - Some functions do size based byte swapping
1898  *				 IO bus.  Size-based byte swapping converts a
1899  *				 multi-byte field between big-endian and
1900  *				 little-endian format.
1949  * Returns the actual number of mappings creates, which may be less than
1951  * is less than the #ttes, the caller may continus to call the function with
1956  *       demap an entry before re-mapping it.
1978  * Returns the actual number of ttes demapped, which may be less than or equal
1979  * to the argument #ttes.  If #ttes demapped is less than #ttes, the caller
2049  * If an error occurs during the read, set RET1 to a non-zero value.  The
2075  * report, do set RET1 to a non-zero value.  Otherwise RET1 is zero.
2102  * non-zero value in RET1.  If the read was successful, return zero in RET1
2106  * Non-significant bits in RET2 are not guaranteed to have any specific value
2107  * and therefore must be ignored.  If RET1 is returned as non-zero, the data
2141  * error report, but return a non-zero value in RET1.  If the write was
2181  * which may be less than or equal to the argument size.  If the return
2182  * value #synced is less than size, the caller must continue to call this
2229  * the queue size.  Each queue entry is 64-bytes long, so f.e. a 32 entry
2230  * queue must be aligned on a 2048 byte real address boundary.  The MSI-EQ
2231  * Head and Tail are initialized so that the MSI-EQ is 'empty'.
2266  * Get the valid state of the MSI-EQ described by the given devhandle and
2281  * Set the valid state of the MSI-EQ described by the given devhandle and
2295  * Get the state of the MSI-EQ described by the given devhandle and
2310  * Set the state of the MSI-EQ described by the given devhandle and
2324  * Get the current MSI EQ queue head for the MSI-EQ described by the
2339  * Set the current MSI EQ queue head for the MSI-EQ described by the
2353  * Get the current MSI EQ queue tail for the MSI-EQ described by the
2504  *			A 32-bit aligned list of pci_devices.
2507  *			real address of a pci_device_list. 32-bit aligned.
2515  *	io_page_list	A 64-bit aligned list of real addresses. Each real
2519  *	io_page_list_p	Real address of an io_page_list, 64-bit aligned.
2524  *			a pagesize and table size supported by the un-derlying
2527  *			Each IOTTE in an IOTSB maps one pagesize-sized page.
2535  *	iotsb_index	Zero-based IOTTE number within an IOTSB.
2573  * If successful, the opaque 64-bit handle iotsb_handle is returned in ret1.
2599  * table. However, the table base address r_addr may contain the value -1 which
2677  * the iommu-address-ranges property in the root complex device node defined
2710  * The io_page_list_p specifies the real address of the 64-bit-aligned list of
2719  * be less than or equal to the argument #iottes. If the function returns
2720  * successfully with a #mapped value less than the requested #iottes then the
2728  * It is implementation-defined whether I/O page real address validity checking
2758  * It is implementation-defined whether I/O page real address validity checking
2780  * The actual number of IOTTEs unmapped is returned in #unmapped and may be less
2783  * If #unmapped is less than #iottes, the caller should continue to invoke this
2830  * be less than or equal to the requested number, #iottes.
2832  * Upon a successful return, #synced is less than #iottes, the caller should
2856  * size.  Each queue entry is 64-bytes, so for example, a 32 entry
2863  * The endpoint's transmit queue is un-configured if num entries is zero.
2872  * to reconfiguring it, or un-configuring it.  Re or un-configuring of a
2873  * non-empty transmit queue behaves exactly as defined above, however it
2875  * will be delivered prior to the re-configuration taking effect.
2950  * size.  Each queue entry is 64-bytes, so for example, a 32 entry
2953  * The endpoint's transmit queue is un-configured if num entries is zero.
3029  * entry, as specified by the LDC_MTE_* bits below, and a 64-bit
3306  *		EBADALIGN	Real address not aligned on 64-byte boundary
3342 /* ncs_request() sub-function numbers */
3365 	 * into/out-of the MAU.
3395  * ARG0:	NCS sub-function
3396  * ARG1:	sub-function argument real address
3397  * ARG2:	size in bytes of sub-function argument
3406  * this HVAPI with the HV_NCS_QCONF sub-function, which defines the
3411  * then invoke the HV_NCS_QTAIL_UPDATE sub-function.  Since only
3416  * The real address of the sub-function argument must be aligned on at
3417  * least an 8-byte boundary.
3420  * offset, into the queue and must be less than or equal the 'num_ents'