include/asm/hypervisor.h

175  * implementated granularity is given by the 'watchdog-resolution'
248  * Start CPU with given CPU ID with PC in %pc and with a real trap
337  * Configure the given queue to be placed at the given base real
338  * address, with the given number of entries.  The number of entries
344  * The specified queue is unconfigured if the number of entries is given
381  * Return the configuration info for the given queue.  The base real
408  * Send a mondo interrupt to the CPUs in the given CPU list with the
409  * 64-bytes at the given data real address.  The data must be 64-byte
445  * Retrieve the current state of the CPU with the given CPU ID.
465  * Set the real trap base address of the local cpu to the given RTBA.
517 /* Page size index.  The value given in the TSB descriptor must correspond
595  * Create a non-permanent mapping using the given TTE, virtual
612  * Demaps the given virtual address in the given mmu context on this
634  *					the given TSB size
646  * array of the given number of TSB descriptions.
648  * Note: The maximum number of TSBs available to a virtual CPU is given by the
669  * array of the given number of TSB descriptions.
688  * Demaps any page mapping of the given virtual address in the given
710  * for the given context for the current virtual CPU.  Any virtual
756  * Create a permanent mapping using the given TTE and virtual address
761  * The behavior is undefined if a TTE with the valid bit clear is given.
816  * Upon successful completion, control will be returned to the given
834  * mmu_map_perm_addr()) at the given virtual address for context 0 on
852  * into the provided buffer.  The size of the buffer is given in ARG1
874  * is given in ARG1 in terms of the number of TSB description entries.
915  * memory address range.  Scrubbing is started at the given real
916  * address, but may not scrub the entire given length.  The actual
944  * the given length may be synced, the actual amount synced is
1175  * and the number of bytes read into the given buffer is provided
1592  *	intr_state	A flag representing the interrupt state for a given
1595  *	intr_enabled	A flag representing the 'enabled' state for a given
1615  * Converts a device specific interrupt number of the given
1634  * by the given sysino.
1667  * Returns current state of the interrupt defined by the given sysino.
1683  * Sets the current state of the interrupt described by the given sysino
1704  * the given sysino.  The CPU value returned is undefined if the target
1722  * Set the target CPU for the interrupt defined by the given sysino.
1932  * Create IOMMU mappings in the sun4v device defined by the given
1934  * tsbnum component of the given tsbid.  The first mapping is created
1935  * in the TSB i ndex defined by the tsbindex component of the given tsbid.
1941  * defined by the given io_page_list_p, which is a pointer to the io_page_list.
1947  * component of the given tsbid must be zero.
1970  * Demap and flush IOMMU mappings in the device defined by the given
1972  * component of the given tsbid, starting at the TSB index defined by the
1973  * tsbindex component of the given tsbid.
1975  * For this version of the spec, the tsbnum of the given tsbid must be zero.
1999  * Read and return the mapping in the device described by the given devhandle
2003  * For this version of the spec, the tsbnum component of the given tsbid
2020  * Create a "special" mapping in the device described by the given devhandle,
2021  * for the given real address and attributes.  Return the IO address in RET1
2040  * Read PCI configuration space for the adapter described by the given
2041  * devhandle.  Read size (1, 2, or 4) bytes of data from the given
2050  * given pci_config_offset must be 'size' aligned.
2068  * Write PCI configuration space for the adapter described by the given
2076  * The given pci_config_offset must be 'size' aligned.
2079  * space described by the given pci_device if necessary to ensure that the
2098  * Attempt to read the IO address given by the given devhandle, real address,
2100  * access operation using the given size.  If an error occurs when reading
2101  * from the given location, do not generate an error report, but return a
2110  * The caller must have permission to read from the given devhandle, real
2135  * Attempt to write data to the IO address given by the given devhandle,
2137  * performed as a single access operation using the given size. Prior to
2140  * If an error occurs when writing to the given location, do not generate an
2153  * The caller must have permission to write to the given devhandle, real
2156  * the given devhandle, pci_device cofiguration space offset 0.
2175  * Synchronize a memory region described by the given real address and size,
2176  * for the device defined by the given devhandle using the direction(s)
2177  * defined by the given io_sync_direction.  The argument size is the size of
2226  * Configure the MSI queue given by the devhandle and msiqid arguments,
2227  * and to be placed at the given real address and be of the given
2250  * by the given devhandle and msiqid.  The base address of the queue
2266  * Get the valid state of the MSI-EQ described by the given devhandle and
2281  * Set the valid state of the MSI-EQ described by the given devhandle and
2282  * msiqid to the given msiqvalid.
2295  * Get the state of the MSI-EQ described by the given devhandle and
2310  * Set the state of the MSI-EQ described by the given devhandle and
2311  * msiqid to the given msiqvalid.
2325  * given devhandle and msiqid.
2340  * given devhandle and msiqid.
2354  * given devhandle and msiqid.
2368  * given devhandle and msinum.
2382  * given devhandle and msinum.
2395  * Get the MSI EQ that the MSI defined by the given devhandle and
2410  * Set the MSI EQ that the MSI defined by the given devhandle and
2424  * Get the state of the MSI defined by the given devhandle and msinum.
2438  * Set the state of the MSI defined by the given devhandle and msinum.
2451  * Get the MSI EQ of the MSG defined by the given devhandle and msgtype.
2464  * Set the MSI EQ of the MSG defined by the given devhandle and msgtype.
2477  * Get the valid/enabled state of the MSG defined by the given
2491  * Set the valid/enabled state of the MSG defined by the given
2517  *			to the pagesize of the given IOTSB.
2673  * This service returns the IOTSB binding, iotsb_handle, for a given pci_device
2853  * given channel ID, to be placed at the given real address, and
2854  * be of the given num entries.  Num entries must be a power of two.
2891  * defined by the given channel ID.  The real address is the currently
2911  * the transmit queue of the LDC endpoint defined by the given channel ID.
2925  * endpoint defined by the given channel ID.  The tail offset specified
2947  * given channel ID, to be placed at the given real address, and
2948  * be of the given num entries.  Num entries must be a power of two.
2983  * defined by the given channel ID.  The real address is the currently
3003  * the receive queue of the LDC endpoint defined by the given channel ID.
3017  * endpoint defined by the given channel ID.  The head offset specified
3065  * Register the MTE table at the given table real address, with the
3066  * specified num entries, for the LDC indicated by the given channel
3080  * for the given channel ID.
3202  * Read the value of the given DRAM/JBUS performance counter/control register.
3215  * Write the given performance reg value to the given DRAM/JBUS
3309  * Enable MMU statistic gathering using the buffer at the given real
3311  * is given in ARG1, and the previously specified buffer real address
3319  * given to the hypervisor or else the statistics will be meaningless.
3421  * argument given in the HV_NCS_QCONF call.