include/asm/fhc.h

1 /* SPDX-License-Identifier: GPL-2.0 */
14 #define CLOCK_PWRSTAT	0x30UL	/* Power status */
15 #define CLOCK_PWRPRES	0x40UL	/* Power presence */
18 #define CLOCK_PWRSTAT2	0x70UL	/* Power status two */
20 #define CLOCK_CTRL_LLED		0x04	/* Left LED, 0 == on */
21 #define CLOCK_CTRL_MLED		0x02	/* Mid LED, 1 == on */
22 #define CLOCK_CTRL_RLED		0x01	/* RIght LED, 1 == on */
30 #define FHC_PREGS_RCS	0x10UL	/* FHC Reset Control/Status Register */
31 #define  FHC_RCS_POR		0x80000000 /* Last reset was a power cycle	*/
32 #define  FHC_RCS_SPOR		0x40000000 /* Last reset was sw power on reset	*/
33 #define  FHC_RCS_SXIR		0x20000000 /* Last reset was sw XIR reset	*/
34 #define  FHC_RCS_BPOR		0x10000000 /* Last reset was due to POR button	*/
35 #define  FHC_RCS_BXIR		0x08000000 /* Last reset was due to XIR button	*/
36 #define  FHC_RCS_WEVENT		0x04000000 /* CPU reset was due to wakeup event	*/
38 #define  FHC_RCS_FENAB		0x01000000 /* Fatal errors elicit system reset	*/
41 #define  FHC_CONTROL_FRST	0x00080000 /* Fatal Error Reset Enable		*/
44 #define  FHC_CONTROL_DCD	0x00008000 /* DC-->DC Converter Disable		*/
47 #define  FHC_CONTROL_AOFF	0x00001000 /* CPU A SRAM/SBD Low Power Mode	*/
48 #define  FHC_CONTROL_BOFF	0x00000800 /* CPU B SRAM/SBD Low Power Mode	*/
49 #define  FHC_CONTROL_PSOFF	0x00000400 /* Turns off this FHC's power supply	*/
52 #define  FHC_CONTROL_LLED	0x00000040 /* 0=Left LED ON			*/
53 #define  FHC_CONTROL_MLED	0x00000020 /* 1=Middle LED ON			*/
69 #define  FHC_JTAG_CTRL_MNONE	0x40000000 /* Indicates no JTAG Master present	 */