Lines Matching +full:multi +full:- +full:address
1 # SPDX-License-Identifier: GPL-2.0
12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
15 On other systems (such as the SH-3 and 4) where an MMU exists,
26 On MMU-less systems, any of these page sizes can be selected
53 hex "Physical memory start address"
57 map the ROM starting at address zero. But the processor
60 The physical memory (RAM) start address will be automatically
89 bool "Support 32-bit physical addressing through PMB"
95 32-bits through the SH-4A PMB. If this is not set, legacy
96 29-bit physical addressing will be used.
116 bool "Non-Uniform Memory Access (NUMA) Support"
122 the address space, each with varying latencies. This enables
186 bool "Multi-core scheduler support"
190 Multi-core scheduler support improves the CPU scheduler's decision
191 making when dealing with multi-core CPU chips at a cost of slightly
209 bool "Write-back"
212 bool "Write-through"
214 Selecting this option will configure the caches in write-through
215 mode, as opposed to the default write-back configuration.
217 Since there's sill some aliasing issues on SH-4, this option will