Lines Matching +full:4 +full:kb +full:- +full:page
1 # SPDX-License-Identifier: GPL-2.0
12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
15 On other systems (such as the SH-3 and 4) where an MMU exists,
26 On MMU-less systems, any of these page sizes can be selected
40 The kernel page allocator limits the size of maximal physically
47 The page size is not necessarily 4KB. Keep this in mind when
89 bool "Support 32-bit physical addressing through PMB"
95 32-bits through the SH-4A PMB. If this is not set, legacy
96 29-bit physical addressing will be used.
103 bool "Support vsyscall page"
107 This will enable support for the kernel mapping a vDSO page
112 For systems with an MMU that can afford to give up a page,
116 bool "Non-Uniform Memory Access (NUMA) Support"
159 prompt "HugeTLB page size"
165 bool "64kB"
169 bool "256kB"
176 bool "4MB"
186 bool "Multi-core scheduler support"
190 Multi-core scheduler support improves the CPU scheduler's decision
191 making when dealing with multi-core CPU chips at a cost of slightly
199 bool "Enable 32KB cache size for SH7705"
209 bool "Write-back"
212 bool "Write-through"
214 Selecting this option will configure the caches in write-through
215 mode, as opposed to the default write-back configuration.
217 Since there's sill some aliasing issues on SH-4, this option will