cpu/sh4a/clock-sh7785.c

69 struct clk div4_clks[DIV4_NR] = {  variable
91 	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
92 	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
93 	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
94 	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
95 	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
96 	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
97 	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
98 	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
99 	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
100 	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
101 	[MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
102 	[MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
103 	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
104 	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
105 	[MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
106 	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
122 	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
123 	CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
124 	CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
125 	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
126 	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
127 	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
128 	CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
129 	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
168 		ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),  in arch_clk_init()