cpu/sh4a/clock-sh7757.c

70 	[DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
71 	[DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
72 	[DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
75 #define MSTPCR0		0xffc80030
76 #define MSTPCR1		0xffc80034
77 #define MSTPCR2		0xffc10028
85 	[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
86 	[MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
89 	[MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 27, 0),
90 	[MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
91 	[MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
92 	[MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
93 	[MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
94 	[MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
95 	[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
96 	[MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
99 	[MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
113 	CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP004]),
123 	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP113]),
127 	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP110]),
130 	CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP102]),
137 	int i, ret = 0;  in arch_clk_init()
139 	for (i = 0; i < ARRAY_SIZE(clks); i++)  in arch_clk_init()