Lines Matching +full:4 +full:wire

18 #define PA_IRLPRI4      (PA_BCR+0x000a) /* Interrupt Priorty 4 */
62 #define PA_SMCR         (PA_BCR+0x0600) /* 2-wire Serial control */
63 #define PA_SMSMADR      (PA_BCR+0x0602) /* 2-wire Serial Slave control */
64 #define PA_SMMR         (PA_BCR+0x0604) /* 2-wire Serial Mode control */
65 #define PA_SMSADR1      (PA_BCR+0x0606) /* 2-wire Serial Address1 control */
66 #define PA_SMTRDR1      (PA_BCR+0x0646) /* 2-wire Serial Data1 control */
87 #define	PA_ZIGIO4	(PA_BCR+0x0012)	/* Zigbee IO control 4 */
114 #define PA_SMCR		(PA_BCR+0x0500)	/* 2-wire Serial control */
115 #define PA_SMSMADR	(PA_BCR+0x0502)	/* 2-wire Serial Slave control */
116 #define PA_SMMR		(PA_BCR+0x0504)	/* 2-wire Serial Mode control */
117 #define PA_SMSADR1	(PA_BCR+0x0506)	/* 2-wire Serial Address1 control */
118 #define PA_SMTRDR1	(PA_BCR+0x0546)	/* 2-wire Serial Data1 control */
176 #define IVDR_CK_ON	4		/* iVDR Clock ON */
186 #define IRQ_EXT1		(HL_FPGA_IRQ_BASE + 4)