Lines Matching +full:0 +full:x0000fc00
10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
12 #define MMU_TTB 0xFF000008 /* Translation table base register */
13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */
15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
17 #define MMUCR 0xFF000010 /* MMU Control Register */
21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000
23 #define MMU_ITLB_DATA_ARRAY 0xF3000000
24 #define MMU_ITLB_DATA_ARRAY2 0xF3800000
26 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
27 #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
28 #define MMU_UTLB_DATA_ARRAY 0xF7000000
29 #define MMU_UTLB_DATA_ARRAY2 0xF7800000
30 #define MMU_PAGE_ASSOC_BIT 0x80
33 #define MMUCR_AT (1 << 0)
35 #define MMUCR_AT (0)
40 #define MMUCR_URB 0x00FC0000
43 #define MMUCR_URC 0x0000FC00
49 #define MMUCR_SE (0)
55 #define MMUCR_AEX (0)
61 #define MMUCR_ME (0)
67 #define MMUCR_SQMD (0)
74 #define TRA 0xff000020
75 #define EXPEVT 0xff000024
76 #define INTEVT 0xff000028