include/asm/watchdog.h

1 /* SPDX-License-Identifier: GPL-2.0+
3  * include/asm-sh/watchdog.h
25  * See cpu-sh2/watchdog.h for explanation of this stupidity..
36  * CKS0-2 supports a number of clock division ratios. At the time the watchdog
37  * is enabled, it defaults to a 41 usec overflow period .. we overload this to
42  * --------------------------------------------
63  * 	sh_wdt_read_cnt - Read from Counter
72  *	sh_wdt_write_cnt - Write to Counter
73  *	@val: Value to write
75  *	Writes the given value @val to the lower byte of the timer counter.
76  *	The upper byte is set manually on each write.
84  *	sh_wdt_write_bst - Write to Counter
85  *	@val: Value to write
87  *	Writes the given value @val to the lower byte of the timer counter.
88  *	The upper byte is set manually on each write.
95  * 	sh_wdt_read_csr - Read from Control/Status Register
105  * 	sh_wdt_write_csr - Write to Control/Status Register
106  * 	@val: Value to write
108  * 	Writes the given value @val to the lower byte of the control/status
109  * 	register. The upper byte is set manually on each write.
117  * 	sh_wdt_read_cnt - Read from Counter
126  *	sh_wdt_write_cnt - Write to Counter
127  *	@val: Value to write
129  *	Writes the given value @val to the lower byte of the timer counter.
130  *	The upper byte is set manually on each write.
138  * 	sh_wdt_read_csr - Read from Control/Status Register
148  * 	sh_wdt_write_csr - Write to Control/Status Register
149  * 	@val: Value to write
151  * 	Writes the given value @val to the lower byte of the control/status
152  * 	register. The upper byte is set manually on each write.