Lines Matching +full:data +full:- +full:transfer

1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include "pci-sh7780.h"
10 #include "pci-sh7751.h"
40 #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
41 #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
45 #define SH4_PCIINTM_TTADIM BIT(14) /* Target-target abort interrupt */
50 #define SH4_PCIINTM_DPEITWM BIT(5) /* Data parity error for target write */
54 #define SH4_PCIINTM_MWPDIM BIT(1) /* Master write data parity error */
55 #define SH4_PCIINTM_MRDPEIM BIT(0) /* Master read data parity error */
57 #define SH4_PCICLR 0x120 /* Error Command/Data */
59 #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
60 #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
61 #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
62 #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
63 #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */
71 #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
72 #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */
80 #define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
81 #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
82 #define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */
84 #define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */
93 #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
96 #define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */
98 #define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */
100 #define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */
102 #define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */
104 #define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */
106 #define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */
147 #define SH4_PCIPDTR 0x204 /* Port Data Register */
154 #define SH4_PCIPDR 0x220 /* Port IO Data Register */
156 /* arch/sh/kernel/drivers/pci/ops-sh4.c */
173 __raw_writel(val, chan->reg_base + reg); in pci_write_reg()
179 return __raw_readl(chan->reg_base + reg); in pci_read_reg()