Lines Matching +full:0 +full:x0c000000

14         case 0: return evt2irq(0x3a0);  in pcibios_map_platform_irq()
15         case 1: return evt2irq(0x3a0);	/* AMD Ethernet controller */  in pcibios_map_platform_irq()
25 #define PCIMCR_MRSET_OFF	0xBFFFFFFF
26 #define PCIMCR_RFSH_OFF		0xFFFFFFFB
58 	bcr1 = bcr1 | 0x00080000;  /* Enable Bit 19, BREQEN */  in pci_fixup_pcic()
61 	bcr1 = bcr1 | 0x40080000;  /* Enable Bit 19 BREQEN, set PCIC to slave */  in pci_fixup_pcic()
72 	PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);  in pci_fixup_pcic()
73 	PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);  in pci_fixup_pcic()
76 	PCIC_WRITE(SH7751_PCICONF1,	0xF39000C7); /* Bus Master, Mem & I/O access */  in pci_fixup_pcic()
77 	PCIC_WRITE(SH7751_PCICONF2,	0x00000000); /* PCI Class code & Revision ID */  in pci_fixup_pcic()
78 	PCIC_WRITE(SH7751_PCICONF4,	0xab000001); /* PCI I/O address (local regs) */  in pci_fixup_pcic()
79 	PCIC_WRITE(SH7751_PCICONF5,	0x0c000000); /* PCI MEM address (local RAM)  */  in pci_fixup_pcic()
80 	PCIC_WRITE(SH7751_PCICONF6,	0xd0000000); /* PCI MEM address (unused)     */  in pci_fixup_pcic()
81 	PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */  in pci_fixup_pcic()
82 	PCIC_WRITE(SH7751_PCILSR0, 0x03f00000);   /* MEM (full 64M exposed)       */  in pci_fixup_pcic()
83 	PCIC_WRITE(SH7751_PCILSR1, 0x00000000);   /* MEM (unused)                 */  in pci_fixup_pcic()
84 	PCIC_WRITE(SH7751_PCILAR0, 0x0c000000);   /* MEM (direct map from PCI)    */  in pci_fixup_pcic()
85 	PCIC_WRITE(SH7751_PCILAR1, 0x00000000);   /* MEM (unused)                 */  in pci_fixup_pcic()
88 	PCIC_WRITE(SH7751_PCICR, 0xa5000001);  in pci_fixup_pcic()
107 	PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));  in pci_fixup_pcic()