Lines Matching +full:0 +full:x1c00
23 #define BCR2 (0xFFFFFF62)
24 #define WCR2 (0xFFFFFF66)
25 #define AREA5_WAIT_CTRL (0x1C00)
26 #define WAIT_STATES_10 (0x7)
30 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
31 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
35 [0] = {
38 .end = PA_EXT5 + 0x1fff,
58 .id = 0,
66 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
100 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); in polaris_initialise()
120 { IRQ0_IRQ, 0, 0, 1, }, /* IRQ0 */
121 { IRQ1_IRQ, 0, 4, 1, }, /* IRQ1 */
142 __raw_writew(0, BCR_ILCRA); in init_polaris_irq()
143 __raw_writew(0, BCR_ILCRB); in init_polaris_irq()
144 __raw_writew(0, BCR_ILCRC); in init_polaris_irq()
145 __raw_writew(0, BCR_ILCRD); in init_polaris_irq()
146 __raw_writew(0, BCR_ILCRE); in init_polaris_irq()
147 __raw_writew(0, BCR_ILCRF); in init_polaris_irq()
148 __raw_writew(0, BCR_ILCRG); in init_polaris_irq()