71 #define REG_W0		(MAX_BPF_JIT_REG + 0)	/* Work register 1 (even) */  macro
75 #define REG_0		REG_W0			/* Register 0 */
106 	[REG_W0]	= 0,
1047 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
1052 			EMIT2(0x1700, REG_W0, REG_W0);  in bpf_jit_insn()
1056 			EMIT4(0xb9970000, REG_W0, src_reg);  in bpf_jit_insn()
1062 			EMIT4(0xb91d0000, REG_W0, src_reg);  in bpf_jit_insn()
1074 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
1079 			EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
1083 			EMIT4(0xb9870000, REG_W0, src_reg);  in bpf_jit_insn()
1089 			EMIT4(0xb90d0000, REG_W0, src_reg);  in bpf_jit_insn()
1099 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
1113 				EMIT2(0x1700, REG_W0, REG_W0);  in bpf_jit_insn()
1117 				EMIT6_DISP_LH(0xe3000000, 0x0097, REG_W0, REG_0,  in bpf_jit_insn()
1124 				EMIT6_DISP_LH(0xe3000000, 0x001d, REG_W0, REG_0,  in bpf_jit_insn()
1132 				EMIT2(0x1700, REG_W0, REG_W0);  in bpf_jit_insn()
1140 				EMIT4(0xb9970000, REG_W0, dst_reg);  in bpf_jit_insn()
1150 				EMIT4(0xb90d0000, REG_W0, dst_reg);  in bpf_jit_insn()
1163 		int rc_reg = BPF_OP(insn->code) == BPF_DIV ? REG_W1 : REG_W0;  in bpf_jit_insn()
1175 				EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
1179 				EMIT6_DISP_LH(0xe3000000, 0x0087, REG_W0, REG_0,  in bpf_jit_insn()
1186 				EMIT6_DISP_LH(0xe3000000, 0x000d, REG_W0, REG_0,  in bpf_jit_insn()
1194 				EMIT4_IMM(0xa7090000, REG_W0, 0);  in bpf_jit_insn()
1202 				EMIT4(0xb9870000, REG_W0, dst_reg);  in bpf_jit_insn()
1212 				EMIT4(0xb90d0000, REG_W0, dst_reg);  in bpf_jit_insn()
1245 			EMIT6_PCREL_RILB(0xc4080000, REG_W0,  in bpf_jit_insn()
1249 			EMIT4(0xb9800000, dst_reg, REG_W0);  in bpf_jit_insn()
1277 			EMIT6_PCREL_RILB(0xc4080000, REG_W0,  in bpf_jit_insn()
1281 			EMIT4(0xb9810000, dst_reg, REG_W0);  in bpf_jit_insn()
1311 			EMIT6_PCREL_RILB(0xc4080000, REG_W0,  in bpf_jit_insn()
1315 			EMIT4(0xb9820000, dst_reg, REG_W0);  in bpf_jit_insn()
1507 		EMIT4_IMM(0xa7080000, REG_W0, (u8) imm);  in bpf_jit_insn()
1510 		EMIT6_DISP_LH(0xe3000000, 0x0072, REG_W0, dst_reg,  in bpf_jit_insn()
1520 		EMIT4_IMM(0xa7080000, REG_W0, (u16) imm);  in bpf_jit_insn()
1523 		EMIT6_DISP_LH(0xe3000000, 0x0070, REG_W0, dst_reg,  in bpf_jit_insn()
1533 		EMIT6_IMM(0xc00f0000, REG_W0, (u32) imm);  in bpf_jit_insn()
1536 		EMIT6_DISP_LH(0xe3000000, 0x0050, REG_W0, dst_reg,  in bpf_jit_insn()
1546 		EMIT6_IMM(0xc0010000, REG_W0, imm);  in bpf_jit_insn()
1549 		EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, dst_reg,  in bpf_jit_insn()
1580 		      (insn->imm & BPF_FETCH) ? src_reg : REG_W0,	\  in bpf_jit_insn()
1620 				      is32 ? 0x0058 : 0x0004, REG_W0, REG_0,  in bpf_jit_insn()
1631 				      REG_W0, src_reg, probe.arena_reg, off);  in bpf_jit_insn()
1636 			EMIT4(is32 ? 0xb9160000 : 0xb9040000, src_reg, REG_W0);  in bpf_jit_insn()
1838 		EMIT4_IMM(0xa7080000, REG_W0, 1);  in bpf_jit_insn()
1840 		EMIT6_DISP_LH(0xeb000000, 0x00fa, REG_W1, REG_W0, REG_15, off);  in bpf_jit_insn()
2483 	load_imm64(jit, REG_W0, tlink->cookie);  in invoke_bpf_prog()
2485 	EMIT6_DISP_LH(0xe3000000, 0x0024, REG_W0, REG_0, REG_15, cookie_off);  in invoke_bpf_prog()