41 	return 0;  in arch_uprobe_pre_xol()
57 		return 0;  in check_per_event()
59 	if (control == 0)  in check_per_event()
62 	if ((control & 0x20200000) && (cause & 0x2000))  in check_per_event()
64 	if (cause & 0x8000) {  in check_per_event()
66 		if ((control & 0x80800000) == 0x80000000)  in check_per_event()
69 		if (((control & 0x80800000) == 0x80800000) &&  in check_per_event()
74 	return 0;  in check_per_event()
90 		int reg = (auprobe->insn[0] & 0xf0) >> 4;  in arch_uprobe_post_xol()
95 		int ilen = insn_length(auprobe->insn[0] >> 8);  in arch_uprobe_post_xol()
107 	return 0;  in arch_uprobe_post_xol()
118 	if (regs->int_code & 0x200) /* Trap during transaction */  in arch_uprobe_exception_notify()
177 	int __rc = 0;					\
192 	int __rc = 0;					\
198 	if (__rc == 0)					\
209 	int __rc = 0;					\
220 		psw_bits((regs)->psw).cc = 0;		\
269 	int rc = 0;  in handle_insn_ril()
277 	case 0xc0:  in handle_insn_ril()
279 		case 0x00: /* larl */  in handle_insn_ril()
284 	case 0xc4:  in handle_insn_ril()
286 		case 0x02: /* llhrl */  in handle_insn_ril()
289 		case 0x04: /* lghrl */  in handle_insn_ril()
292 		case 0x05: /* lhrl */  in handle_insn_ril()
295 		case 0x06: /* llghrl */  in handle_insn_ril()
298 		case 0x08: /* lgrl */  in handle_insn_ril()
301 		case 0x0c: /* lgfrl */  in handle_insn_ril()
304 		case 0x0d: /* lrl */  in handle_insn_ril()
307 		case 0x0e: /* llgfrl */  in handle_insn_ril()
310 		case 0x07: /* sthrl */  in handle_insn_ril()
313 		case 0x0b: /* stgrl */  in handle_insn_ril()
316 		case 0x0f: /* strl */  in handle_insn_ril()
321 	case 0xc6:  in handle_insn_ril()
323 		case 0x04: /* cghrl */  in handle_insn_ril()
326 		case 0x05: /* chrl */  in handle_insn_ril()
329 		case 0x06: /* clghrl */  in handle_insn_ril()
332 		case 0x07: /* clhrl */  in handle_insn_ril()
335 		case 0x08: /* cgrl */  in handle_insn_ril()
338 		case 0x0a: /* clgrl */  in handle_insn_ril()
341 		case 0x0c: /* cgfrl */  in handle_insn_ril()
344 		case 0x0d: /* crl */  in handle_insn_ril()
347 		case 0x0e: /* clgfrl */  in handle_insn_ril()
350 		case 0x0f: /* clrl */  in handle_insn_ril()
359 		regs->int_code = ilen << 16 | 0x0001;  in handle_insn_ril()
363 		regs->int_code = ilen << 16 | 0x0006;  in handle_insn_ril()
367 		regs->int_code = ilen << 16 | 0x0005;  in handle_insn_ril()