include/asm/processor.h

1 /* SPDX-License-Identifier: GPL-2.0 */
8  *  Derived from "include/asm-i386/processor.h"
34 #include <asm/fpu-types.h>
59 	return (struct pcpu *)(get_lowcore()->pcpu);  in this_pcpu()
64 	this_pcpu()->flags |= (1UL << flag);  in set_cpu_flag()
69 	this_pcpu()->flags &= ~(1UL << flag);  in clear_cpu_flag()
74 	return this_pcpu()->flags & (1UL << flag);  in test_cpu_flag()
106 	asm volatile("stidp %0" : "=Q" (*ptr));  in get_cpu_id()
113 	asm volatile("stpt	%[timer]" : [timer] "=Q" (timer));  in get_cpu_timer()
134 #define TASK_SIZE_MAX		(-PAGE_SIZE)
138 #define STACK_TOP		(VDSO_LIMIT - vdso_size() - PAGE_SIZE)
139 #define STACK_TOP_MAX		(_REGION2_SIZE - vdso_size() - PAGE_SIZE)
150 	count = erase_high - erase_low;  in __stackleak_poison()
156 		"	aghi	%[count],-(8+1)\n"  in __stackleak_poison()
161 		"	mvc	8(256-8,%[addr]),0(%[addr])\n"  in __stackleak_poison()
190 	unsigned long gmap_addr;		/* address of last gmap fault. */
191 	unsigned int gmap_write_flag;		/* gmap fault write indication */
192 	unsigned int gmap_int_code;		/* int code of last gmap fault */
197 	/* Per-thread information related to debugging */
202 	unsigned long last_break;		/* last breaking-event-address. */
220  * - abort each transaction at a random instruction before TEND if set.
221  * - abort random transactions at a random instruction if cleared.
238 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_EA | PSW_MASK_BA;	\
239 	regs->psw.addr	= new_psw;					\
240 	regs->gprs[15]	= new_stackp;					\
245 	regs->psw.mask	= PSW_USER_BITS | PSW_MASK_BA;			\
246 	regs->psw.addr	= new_psw;					\
247 	regs->gprs[15]	= new_stackp;					\
265         (task_stack_page(tsk) + THREAD_SIZE) - 1)
266 #define KSTK_EIP(tsk)	(task_pt_regs(tsk)->psw.addr)
267 #define KSTK_ESP(tsk)	(task_pt_regs(tsk)->gprs[15])
270 #define is_ri_task(tsk) (!!(tsk)->thread.ri_cb)
285 	unsigned long ksp = get_lowcore()->kernel_stack;  in on_thread_stack()
287 	return !((ksp ^ current_stack_pointer) & ~(THREAD_SIZE - 1));  in on_thread_stack()
294 	asm volatile("stap %0" : "=Q" (cpu_address));  in stap()
321 	asm volatile("lpswe %0" : : "Q" (psw) : "cc");  in __load_psw()
340 		: "=&d" (addr), "=Q" (psw.addr) : "Q" (psw) : "memory", "cc");  in __load_psw_mask()
393 	mask = (psw.mask & PSW_MASK_EA) ? -1UL :  in __rewind_psw()
394 	       (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :  in __rewind_psw()
395 					  (1UL << 24) - 1;  in __rewind_psw()
396 	return (psw.addr - ilc) & mask;  in __rewind_psw()
416 	return arch_irqs_disabled_flags(regs->psw.mask);  in regs_irqs_disabled()