include/asm/fpu-insn-asm.h

286 .macro	VLVG	v, gr, disp, m
291 	.word	(b2 << 12) | (\disp)
317 .macro	VL	v, disp, index="%r0", base
322 	.word	(b2 << 12) | (\disp)
327 .macro	VLEx	vr1, disp, index="%r0", base, m3, opc
332 	.word	(b2 << 12) | (\disp)
335 .macro	VLEB	vr1, disp, index="%r0", base, m3
336 	VLEx	\vr1, \disp, \index, \base, \m3, 0x00
338 .macro	VLEH	vr1, disp, index="%r0", base, m3
339 	VLEx	\vr1, \disp, \index, \base, \m3, 0x01
341 .macro	VLEF	vr1, disp, index="%r0", base, m3
342 	VLEx	\vr1, \disp, \index, \base, \m3, 0x03
344 .macro	VLEG	vr1, disp, index="%r0", base, m3
345 	VLEx	\vr1, \disp, \index, \base, \m3, 0x02
369 .macro	VLGV	gr, vr, disp, base="%r0", m
374 	.word	(b2 << 12) | (\disp)
377 .macro	VLGVB	gr, vr, disp, base="%r0"
378 	VLGV	\gr, \vr, \disp, \base, 0
380 .macro	VLGVH	gr, vr, disp, base="%r0"
381 	VLGV	\gr, \vr, \disp, \base, 1
383 .macro	VLGVF	gr, vr, disp, base="%r0"
384 	VLGV	\gr, \vr, \disp, \base, 2
386 .macro	VLGVG	gr, vr, disp, base="%r0"
387 	VLGV	\gr, \vr, \disp, \base, 3
391 .macro	VLM	vfrom, vto, disp, base, hint=3
396 	.word	(b2 << 12) | (\disp)
401 .macro	VST	vr1, disp, index="%r0", base
406 	.word	(b2 << 12) | (\disp)
411 	.macro	VSTBR	vr1, disp, index="%r0", base, m
416 	.word	(b2 << 12) | (\disp)
419 .macro	VSTBRH	vr1, disp, index="%r0", base
420 	VSTBR	\vr1, \disp, \index, \base, 1
422 .macro	VSTBRF	vr1, disp, index="%r0", base
423 	VSTBR	\vr1, \disp, \index, \base, 2
425 .macro	VSTBRG	vr1, disp, index="%r0", base
426 	VSTBR	\vr1, \disp, \index, \base, 3
428 .macro	VSTBRQ	vr1, disp, index="%r0", base
429 	VSTBR	\vr1, \disp, \index, \base, 4
433 .macro	VSTM	vfrom, vto, disp, base, hint=3
438 	.word	(b2 << 12) | (\disp)
547 .macro VLL	v, gr, disp, base
552 	.word	(b2 << 12) | (\disp)
557 .macro VSTL	v, gr, disp, base
562 	.word	(b2 << 12) | (\disp)
722 .macro	VERLL	vr1, vr3, disp, base="%r0", m4
727 	.word	(b2 << 12) | (\disp)
730 .macro	VERLLB	vr1, vr3, disp, base="%r0"
731 	VERLL	\vr1, \vr3, \disp, \base, 0
733 .macro	VERLLH	vr1, vr3, disp, base="%r0"
734 	VERLL	\vr1, \vr3, \disp, \base, 1
736 .macro	VERLLF	vr1, vr3, disp, base="%r0"
737 	VERLL	\vr1, \vr3, \disp, \base, 2
739 .macro	VERLLG	vr1, vr3, disp, base="%r0"
740 	VERLL	\vr1, \vr3, \disp, \base, 3