include/asm/fpu-insn-asm.h

100 	.ifc \vxr,%v2
201  * @v2:		Vector register designated operand whose MSB is stored in
211  * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
212  * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
219 .macro	RXB	rxb v1 v2=0 v3=0 v4=0
224 	.if \v2 & 0x10
239  * @v2:		Second vector register designated operand (for RXB)
243  * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
246 .macro	MRXB	m v1 v2=0 v3=0 v4=0
248 	RXB	rxb, \v1, \v2, \v3, \v4
257  * @v2:		Second vector register designated operand (for RXB)
261  * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
264 .macro	MRXBOPC	m opc v1 v2=0 v3=0 v4=0
265 	MRXB	\m, \v1, \v2, \v3, \v4
308 .macro	VLR	v1, v2
310 	VX_NUM	v2, \v2
311 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
313 	MRXBOPC	0, 0x56, v1, v2
445 	VX_NUM	v2, \vr2
448 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
450 	MRXBOPC	(v4&15), 0x8C, v1, v2, v3, v4
456 	VX_NUM	v2, \vr2
457 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
459 	MRXBOPC	\m3, 0xD4, v1, v2
474 	VX_NUM	v2, \vr2
476 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
478 	MRXBOPC	\m4, 0x84, v1, v2, v3
505 	VX_NUM	v2, \vr2
507 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
509 	MRXBOPC	\m4, 0x61, v1, v2, v3
527 	VX_NUM	v2, \vr2
529 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
531 	MRXBOPC	\m4, 0x60, v1, v2, v3
571 	VX_NUM	v2, \vr2
573 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
575 	MRXBOPC	0, 0x68, v1, v2, v3
581 	VX_NUM	v2, \vr2
583 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
585 	MRXBOPC 0, 0x66, v1, v2, v3
591 	VX_NUM	v2, \vr2
593 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
595 	MRXBOPC	0, 0x6D, v1, v2, v3
601 	VX_NUM	v2, \vr2
603 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
605 	MRXBOPC	\m4, 0xB4, v1, v2, v3
623 	VX_NUM	v2, \vr2
626 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
628 	MRXBOPC	(v4&15), 0xBC, v1, v2, v3, v4
646 	VX_NUM	v2, \vr2
648 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
650 	MRXBOPC	0, 0x7D, v1, v2, v3
676 	VX_NUM	v2, \vr2
678 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
680 	MRXBOPC	\m4, 0xF3, v1, v2, v3
701 	VX_NUM	v2, \vr2
703 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
705 	MRXBOPC \m4, 0x7A, v1, v2, v3
746 	VX_NUM	v2, \vr2
748 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
750 	MRXBOPC	0, 0x77, v1, v2, v3