include/asm/fpu-insn-asm.h

40 		\opd = 3
103 	.ifc \vxr,%v3
104 		\opd = 3
204  * @v3:		Vector register designated operand whose MSB is stored in
208  *		RXB bit 3 (instruction bit 39) and whose remaining bits
211  * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
212  * correspond to @v1, @v2, @v3, and @v4. But there are exceptions, such as but
219 .macro	RXB	rxb v1 v2=0 v3=0 v4=0
227 	.if \v3 & 0x10
240  * @v3:		Third vector register designated operand (for RXB)
243  * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
246 .macro	MRXB	m v1 v2=0 v3=0 v4=0
248 	RXB	rxb, \v1, \v2, \v3, \v4
258  * @v3:		Third vector register designated operand (for RXB)
261  * Note: For @v1, @v2, @v3, and @v4 also refer to the RXB macro
264 .macro	MRXBOPC	m opc v1 v2=0 v3=0 v4=0
265 	MRXB	\m, \v1, \v2, \v3, \v4
304 	VLVG	\v, \gr, \index, 3
372 	VX_NUM	v3, \vr
373 	.word	0xE700 | (r1 << 4) | (v3&15)
375 	MRXBOPC	\m, 0x21, 0, v3
387 	VLGV	\gr, \vr, \disp, \base, 3
391 .macro	VLM	vfrom, vto, disp, base, hint=3
393 	VX_NUM	v3, \vto
395 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
397 	MRXBOPC	\hint, 0x36, v1, v3
426 	VSTBR	\vr1, \disp, \index, \base, 3
433 .macro	VSTM	vfrom, vto, disp, base, hint=3
435 	VX_NUM	v3, \vto
437 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
439 	MRXBOPC	\hint, 0x3E, v1, v3
446 	VX_NUM	v3, \vr3
449 	.word	((v3&15) << 12)
450 	MRXBOPC	(v4&15), 0x8C, v1, v2, v3, v4
475 	VX_NUM	v3, \vr3
477 	.word	((v3&15) << 12)
478 	MRXBOPC	\m4, 0x84, v1, v2, v3
484 	VX_NUM	v3, \vr3
485 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
487 	MRXBOPC	\m4, 0x4D, v1, v3
499 	VREP	\vr1, \vr3, \imm2, 3
506 	VX_NUM	v3, \vr3
508 	.word	((v3&15) << 12)
509 	MRXBOPC	\m4, 0x61, v1, v2, v3
521 	VMRH	\vr1, \vr2, \vr3, 3
528 	VX_NUM	v3, \vr3
530 	.word	((v3&15) << 12)
531 	MRXBOPC	\m4, 0x60, v1, v2, v3
543 	VMRL	\vr1, \vr2, \vr3, 3
572 	VX_NUM	v3, \vr3
574 	.word	((v3&15) << 12)
575 	MRXBOPC	0, 0x68, v1, v2, v3
582 	VX_NUM	v3, \vr3
584 	.word	((v3&15) << 12)
585 	MRXBOPC 0, 0x66, v1, v2, v3
592 	VX_NUM	v3, \vr3
594 	.word	((v3&15) << 12)
595 	MRXBOPC	0, 0x6D, v1, v2, v3
602 	VX_NUM	v3, \vr3
604 	.word	((v3&15) << 12)
605 	MRXBOPC	\m4, 0xB4, v1, v2, v3
617 	VGFM	\vr1, \vr2, \vr3, 3
624 	VX_NUM	v3, \vr3
627 	.word	((v3&15) << 12) | (\m5 << 8)
628 	MRXBOPC	(v4&15), 0xBC, v1, v2, v3, v4
640 	VGFMA	\vr1, \vr2, \vr3, \vr4, 3
647 	VX_NUM	v3, \vr3
649 	.word	((v3&15) << 12)
650 	MRXBOPC	0, 0x7D, v1, v2, v3
670 	VREP	\vr1, \imm2, 3
677 	VX_NUM	v3, \vr3
679 	.word	((v3&15) << 12)
680 	MRXBOPC	\m4, 0xF3, v1, v2, v3
692 	VA	\vr1, \vr2, \vr3, 3
702 	VX_NUM	v3, \vr3
704 	.word	((v3&15) << 12)
705 	MRXBOPC \m4, 0x7A, v1, v2, v3
718 	VESRAV	\vr1, \vr2, \vr3, 3
724 	VX_NUM	v3, \vr3
726 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
728 	MRXBOPC	\m4, 0x33, v1, v3
740 	VERLL	\vr1, \vr3, \disp, \base, 3
747 	VX_NUM	v3, \vr3
749 	.word	((v3&15) << 12) | (\imm4)
750 	MRXBOPC	0, 0x77, v1, v2, v3