include/asm/fpu-insn-asm.h

1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/fpu-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
34 		\opd = 1
76 		\opd = 15
83 /* VX_NUM - Retrieve vector register number
98 		\opd = 1
140 		\opd = 15
195 /* RXB - Compute most significant bit used vector registers
200  *		are stored in instruction bits 8-11.
202  *		RXB bit 1 (instruction bit 37) and whose remaining bits
203  *		are stored in instruction bits 12-15.
206  *		are stored in instruction bits 16-19.
209  *		are stored in instruction bits 32-35.
211  * Note: In most vector instruction formats [1] V1, V2, V3, and V4 directly
213  * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
216  * [1] IBM z/Architecture Principles of Operation, chapter "Program
235 /* MRXB - Generate Element Size Control and RXB value
252 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
274 	.word	(0xE700 | ((v1&15) << 4))
290 	.word	0xE700 | ((v1&15) << 4) | r3
298 	VLVG	\v, \gr, \index, 1
311 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
321 	.word	0xE700 | ((v1&15) << 4) | x2
331 	.word	0xE700 | ((v1&15) << 4) | x2
351 	.word	0xE700 | ((v1&15) << 4)
373 	.word	0xE700 | (r1 << 4) | (v3&15)
381 	VLGV	\gr, \vr, \disp, \base, 1
395 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
405 	.word	0xE700 | ((v1&15) << 4) | (x2&15)
415 	.word	0xE600 | ((v1&15) << 4) | (x2&15)
420 	VSTBR	\vr1, \disp, \index, \base, 1
437 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
448 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
449 	.word	((v3&15) << 12)
450 	MRXBOPC	(v4&15), 0x8C, v1, v2, v3, v4
457 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
465 	VUPLL	\vr1, \vr2, 1
476 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
477 	.word	((v3&15) << 12)
485 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
493 	VREP	\vr1, \vr3, \imm2, 1
507 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
508 	.word	((v3&15) << 12)
515 	VMRH	\vr1, \vr2, \vr3, 1
529 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
530 	.word	((v3&15) << 12)
537 	VMRL	\vr1, \vr2, \vr3, 1
551 	.word	0xE700 | ((v1&15) << 4) | r3
561 	.word	0xE700 | ((v1&15) << 4) | r3
573 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
574 	.word	((v3&15) << 12)
583 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
584 	.word	((v3&15) << 12)
593 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
594 	.word	((v3&15) << 12)
603 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
604 	.word	((v3&15) << 12)
611 	VGFM	\vr1, \vr2, \vr3, 1
626 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
627 	.word	((v3&15) << 12) | (\m5 << 8)
628 	MRXBOPC	(v4&15), 0xBC, v1, v2, v3, v4
634 	VGFMA	\vr1, \vr2, \vr3, \vr4, 1
648 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
649 	.word	((v3&15) << 12)
656 	.word	0xE700 | ((v1&15) << 4)
664 	VREPI	\vr1, \imm2, 1
678 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
679 	.word	((v3&15) << 12)
686 	VA	\vr1, \vr2, \vr3, 1
703 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
704 	.word	((v3&15) << 12)
712 	VESRAV	\vr1, \vr2, \vr3, 1
726 	.word	0xE700 | ((v1&15) << 4) | (v3&15)
734 	VERLL	\vr1, \vr3, \disp, \base, 1
748 	.word	0xE700 | ((v1&15) << 4) | (v2&15)
749 	.word	((v3&15) << 12) | (\imm4)