Lines Matching +full:0 +full:- +full:15
1 /* SPDX-License-Identifier: GPL-2.0 */
16 #error only <asm/fpu-insn.h> can be included directly
23 /* GR_NUM - Retrieve general-purpose register number
31 \opd = 0
76 \opd = 15
83 /* VX_NUM - Retrieve vector register number
95 \opd = 0
140 \opd = 15
195 /* RXB - Compute most significant bit used vector registers
199 * RXB bit 0 (instruction bit 36) and whose remaining bits
200 * are stored in instruction bits 8-11.
203 * are stored in instruction bits 12-15.
206 * are stored in instruction bits 16-19.
209 * are stored in instruction bits 32-35.
213 * not limited to the vector instruction formats VRR-g, VRR-h, VRS-a, VRS-d,
219 .macro RXB rxb v1 v2=0 v3=0 v4=0
220 \rxb = 0
221 .if \v1 & 0x10
222 \rxb = \rxb | 0x08
224 .if \v2 & 0x10
225 \rxb = \rxb | 0x04
227 .if \v3 & 0x10
228 \rxb = \rxb | 0x02
230 .if \v4 & 0x10
231 \rxb = \rxb | 0x01
235 /* MRXB - Generate Element Size Control and RXB value
246 .macro MRXB m v1 v2=0 v3=0 v4=0
247 rxb = 0
252 /* MRXBOPC - Generate Element Size Control, RXB, and final Opcode fields
264 .macro MRXBOPC m opc v1 v2=0 v3=0 v4=0
274 .word (0xE700 | ((v1&15) << 4))
276 MRXBOPC 0, 0x44, v1
279 VGBM \vxr, 0
282 VGBM \vxr, 0xFFFF
290 .word 0xE700 | ((v1&15) << 4) | r3
292 MRXBOPC \m, 0x22, v1
295 VLVG \v, \gr, \index, \base, 0
311 .word 0xE700 | ((v1&15) << 4) | (v2&15)
312 .word 0
313 MRXBOPC 0, 0x56, v1, v2
321 .word 0xE700 | ((v1&15) << 4) | x2
323 MRXBOPC 0, 0x06, v1
331 .word 0xE700 | ((v1&15) << 4) | x2
336 VLEx \vr1, \disp, \index, \base, \m3, 0x00
339 VLEx \vr1, \disp, \index, \base, \m3, 0x01
342 VLEx \vr1, \disp, \index, \base, \m3, 0x03
345 VLEx \vr1, \disp, \index, \base, \m3, 0x02
351 .word 0xE700 | ((v1&15) << 4)
356 VLEIx \vr1, \imm2, \index, 0x40
359 VLEIx \vr1, \imm2, \index, 0x41
362 VLEIx \vr1, \imm2, \index, 0x43
365 VLEIx \vr1, \imm2, \index, 0x42
373 .word 0xE700 | (r1 << 4) | (v3&15)
375 MRXBOPC \m, 0x21, 0, v3
378 VLGV \gr, \vr, \disp, \base, 0
395 .word 0xE700 | ((v1&15) << 4) | (v3&15)
397 MRXBOPC \hint, 0x36, v1, v3
405 .word 0xE700 | ((v1&15) << 4) | (x2&15)
407 MRXBOPC 0, 0x0E, v1
415 .word 0xE600 | ((v1&15) << 4) | (x2&15)
417 MRXBOPC \m, 0x0E, v1
437 .word 0xE700 | ((v1&15) << 4) | (v3&15)
439 MRXBOPC \hint, 0x3E, v1, v3
448 .word 0xE700 | ((v1&15) << 4) | (v2&15)
449 .word ((v3&15) << 12)
450 MRXBOPC (v4&15), 0x8C, v1, v2, v3, v4
457 .word 0xE700 | ((v1&15) << 4) | (v2&15)
458 .word 0x0000
459 MRXBOPC \m3, 0xD4, v1, v2
462 VUPLL \vr1, \vr2, 0
476 .word 0xE700 | ((v1&15) << 4) | (v2&15)
477 .word ((v3&15) << 12)
478 MRXBOPC \m4, 0x84, v1, v2, v3
485 .word 0xE700 | ((v1&15) << 4) | (v3&15)
487 MRXBOPC \m4, 0x4D, v1, v3
490 VREP \vr1, \vr3, \imm2, 0
507 .word 0xE700 | ((v1&15) << 4) | (v2&15)
508 .word ((v3&15) << 12)
509 MRXBOPC \m4, 0x61, v1, v2, v3
512 VMRH \vr1, \vr2, \vr3, 0
529 .word 0xE700 | ((v1&15) << 4) | (v2&15)
530 .word ((v3&15) << 12)
531 MRXBOPC \m4, 0x60, v1, v2, v3
534 VMRL \vr1, \vr2, \vr3, 0
551 .word 0xE700 | ((v1&15) << 4) | r3
553 MRXBOPC 0, 0x37, v1
561 .word 0xE700 | ((v1&15) << 4) | r3
563 MRXBOPC 0, 0x3f, v1
573 .word 0xE700 | ((v1&15) << 4) | (v2&15)
574 .word ((v3&15) << 12)
575 MRXBOPC 0, 0x68, v1, v2, v3
583 .word 0xE700 | ((v1&15) << 4) | (v2&15)
584 .word ((v3&15) << 12)
585 MRXBOPC 0, 0x66, v1, v2, v3
593 .word 0xE700 | ((v1&15) << 4) | (v2&15)
594 .word ((v3&15) << 12)
595 MRXBOPC 0, 0x6D, v1, v2, v3
603 .word 0xE700 | ((v1&15) << 4) | (v2&15)
604 .word ((v3&15) << 12)
605 MRXBOPC \m4, 0xB4, v1, v2, v3
608 VGFM \vr1, \vr2, \vr3, 0
626 .word 0xE700 | ((v1&15) << 4) | (v2&15)
627 .word ((v3&15) << 12) | (\m5 << 8)
628 MRXBOPC (v4&15), 0xBC, v1, v2, v3, v4
631 VGFMA \vr1, \vr2, \vr3, \vr4, 0
648 .word 0xE700 | ((v1&15) << 4) | (v2&15)
649 .word ((v3&15) << 12)
650 MRXBOPC 0, 0x7D, v1, v2, v3
656 .word 0xE700 | ((v1&15) << 4)
658 MRXBOPC \m3, 0x45, v1
661 VREPI \vr1, \imm2, 0
678 .word 0xE700 | ((v1&15) << 4) | (v2&15)
679 .word ((v3&15) << 12)
680 MRXBOPC \m4, 0xF3, v1, v2, v3
683 VA \vr1, \vr2, \vr3, 0
703 .word 0xE700 | ((v1&15) << 4) | (v2&15)
704 .word ((v3&15) << 12)
705 MRXBOPC \m4, 0x7A, v1, v2, v3
709 VESRAV \vr1, \vr2, \vr3, 0
726 .word 0xE700 | ((v1&15) << 4) | (v3&15)
728 MRXBOPC \m4, 0x33, v1, v3
731 VERLL \vr1, \vr3, \disp, \base, 0
748 .word 0xE700 | ((v1&15) << 4) | (v2&15)
749 .word ((v3&15) << 12) | (\imm4)
750 MRXBOPC 0, 0x77, v1, v2, v3