riscv/lib/crc32.c

1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <asm/alternative-macros.h>
19  * Refer to https://www.corsix.org/content/barrett-reduction-polynomials for
23  * let "-" denotes polynomial sub (XOR)
26  * let "S" denotes source data, XLEN bit wide
28  * let "T" denotes 2^(XLEN+32)
29  * let "QT" denotes quotient of T/P, with the bit for 2^XLEN being implicit
32  * => S * (2^32) - S * (2^32) / P * P
36  * => lowest 32 bits of: S * quotient / 2^XLEN * P
45 /* Slide by XLEN bits per iteration */
48 /* Each below polynomial quotient has an implicit bit for 2^XLEN */
50 /* Polynomial quotient of (2^(XLEN+32))/CRC32_POLY, in LE format */
53 /* Polynomial quotient of (2^(XLEN+32))/CRC32C_POLY, in LE format */
56 /* Polynomial quotient of (2^(XLEN+32))/CRC32_POLY, in BE format, it should be
57  * the same as the bit-reversed version of CRC32_POLY_QT_LE
73 		      "clmul	%0, %1, %2\n"  in crc32_le_zbc()
74 		      "slli	%0, %0, 1\n"  in crc32_le_zbc()
75 		      "xor	%0, %0, %1\n"  in crc32_le_zbc()
111 		      "clmul	%0, %1, %2\n"  in crc32_le_zbc()
112 		      "slli	%0, %0, 1\n"  in crc32_le_zbc()
113 		      "xor	%0, %0, %1\n"  in crc32_le_zbc()
139 		      "clmulh	%0, %1, %2\n"  in crc32_be_zbc()
140 		      "xor	%0, %0, %1\n"  in crc32_be_zbc()
151 #define STEP		(1 << STEP_ORDER)
152 #define OFFSET_MASK	(STEP - 1)
165 		s = ((unsigned long)*p++ << (__riscv_xlen - 8)) | (s >> 8);  in crc32_le_unaligned()
167 	s ^= (unsigned long)crc << (__riscv_xlen - bits);  in crc32_le_unaligned()
187 			     RISCV_ISA_EXT_ZBC, 1)  in crc32_le_generic()
193 		head_len = min(STEP - offset, len);  in crc32_le_generic()
196 		len -= head_len;  in crc32_le_generic()
244 		s ^= crc >> (32 - bits);  in crc32_be_unaligned()
247 		s ^= (unsigned long)crc << (bits - 32);  in crc32_be_unaligned()
263 			     RISCV_ISA_EXT_ZBC, 1)  in crc32_be()
269 		head_len = min(STEP - offset, len);  in crc32_be()
272 		len -= head_len;  in crc32_be()