1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <asm/entry-common.h>
94 #define XLEN				64  macro
97 #define XLEN				32  macro
99 #define REGBYTES			(1 << LOG_REGBYTES)
100 #define XLEN_MINUS_16			((XLEN) - 16)
107 #define RV_X(x, s, n)			(((x) >> (s)) & ((1 << (n)) - 1))
108 #define RVC_LW_IMM(x)			((RV_X(x, 6, 1) << 2) | \
110 					 (RV_X(x, 5, 1) << 6))
114 					 (RV_X(x, 12, 1) << 5) | \
117 					 (RV_X(x, 12, 1) << 5) | \
128 	((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
131 	((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
134 	(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
154 #define PRECISION_D 1
168 	regs->status |= SR_FS_DIRTY;  in set_f32_rd()
186 	regs->status |= SR_FS_DIRTY;  in set_f64_rd()
201 	regs->status |= SR_FS_DIRTY;  in get_f64_rs()
216 	regs->status |= SR_FS_DIRTY;  in get_f64_rs()
232 	regs->status |= SR_FS_DIRTY;  in get_f32_rs()
287 			return -EFAULT;  in get_insn()
299 			return -EFAULT;  in get_insn()
305 			return -EFAULT;  in get_insn()
326 int unaligned_enabled __read_mostly = 1;	/* Enabled by default */
331 	unsigned long epc = regs->epc;  in handle_misaligned_load()
333 	unsigned long addr = regs->badaddr;  in handle_misaligned_load()
336 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);  in handle_misaligned_load()
343 		return -1;  in handle_misaligned_load()
345 	if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))  in handle_misaligned_load()
346 		return -1;  in handle_misaligned_load()
349 		return -1;  in handle_misaligned_load()
351 	regs->epc = 0;  in handle_misaligned_load()
355 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
359 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
364 		fp = 1;  in handle_misaligned_load()
367 		fp = 1;  in handle_misaligned_load()
371 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
377 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
382 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
386 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
391 		shift = 8 * (sizeof(unsigned long) - len);  in handle_misaligned_load()
393 		fp = 1;  in handle_misaligned_load()
397 		fp = 1;  in handle_misaligned_load()
401 		fp = 1;  in handle_misaligned_load()
405 		fp = 1;  in handle_misaligned_load()
409 		regs->epc = epc;  in handle_misaligned_load()
410 		return -1;  in handle_misaligned_load()
414 		return -EOPNOTSUPP;  in handle_misaligned_load()
419 			return -1;  in handle_misaligned_load()
431 	regs->epc = epc + INSN_LEN(insn);  in handle_misaligned_load()
439 	unsigned long epc = regs->epc;  in handle_misaligned_store()
441 	unsigned long addr = regs->badaddr;  in handle_misaligned_store()
444 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);  in handle_misaligned_store()
447 		return -1;  in handle_misaligned_store()
449 	if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS))  in handle_misaligned_store()
450 		return -1;  in handle_misaligned_store()
453 		return -1;  in handle_misaligned_store()
455 	regs->epc = 0;  in handle_misaligned_store()
466 		fp = 1;  in handle_misaligned_store()
470 		fp = 1;  in handle_misaligned_store()
490 		fp = 1;  in handle_misaligned_store()
494 		fp = 1;  in handle_misaligned_store()
499 		fp = 1;  in handle_misaligned_store()
503 		fp = 1;  in handle_misaligned_store()
508 		regs->epc = epc;  in handle_misaligned_store()
509 		return -1;  in handle_misaligned_store()
513 		return -EOPNOTSUPP;  in handle_misaligned_store()
517 			return -1;  in handle_misaligned_store()
522 	regs->epc = epc + INSN_LEN(insn);  in handle_misaligned_store()
536 		"       "REG_L" %[tmp], 1(%[ptr])\n"  in check_unaligned_access_emulated()