include/asm/insn.h

11 #define RV_INSN_FUNCT3_MASK	GENMASK(14, 12)
12 #define RV_INSN_FUNCT3_OPOFF	12
23 #define RV_I_IMM_SIGN_OFF	12
31 #define RV_J_IMM_19_12_OPOFF	12
35 #define RV_J_IMM_19_12_OFF	12
47 #define RV_U_IMM_31_12_MASK	GENMASK(31, 12)
54 #define RV_B_IMM_SIGN_OFF	12
70 #define RVC_J_IMM_SIGN_OPOFF	12
95 #define RVC_B_IMM_SIGN_OPOFF	12
110 #define RVC_INSN_FUNCT4_MASK	GENMASK(15, 12)
111 #define RVC_INSN_FUNCT4_OPOFF	12
144 #define RVG_SYSTEM_CSR_MASK	GENMASK(12, 0)
147 #define RVFDQ_FL_FS_WIDTH_OFF	12
169 /* parts of funct3 code for I, M, A extension*/
290 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
358  * Get the immediate from a J-type instruction.
369  * Update a J-type instruction with an immediate value.
376 	/* drop the old IMMs, all jal IMM bits sit at 31:12 */  in riscv_insn_insert_jtype_imm()
377 	*insn &= ~GENMASK(31, 12);  in riscv_insn_insert_jtype_imm()
385  * Put together one immediate from a U-type and I-type instruction pair.
387  * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]
388  * being zero, while the I-type contains a 12bit immediate.
407  * Update a set of two instructions (U-type + I-type) with an immediate value.
410  * a 20bit upper immediate representing bits[31:12], while the I-type
411  * instruction contains a 12bit immediate representing bits[11:0].