Lines Matching full:stgcrg
576 clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
577 <&stgcrg JH7110_STGCLK_USB0_STB>,
578 <&stgcrg JH7110_STGCLK_USB0_APB>,
579 <&stgcrg JH7110_STGCLK_USB0_AXI>,
580 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
582 resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
583 <&stgcrg JH7110_STGRST_USB0_APB>,
584 <&stgcrg JH7110_STGRST_USB0_AXI>,
585 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
606 <&stgcrg JH7110_STGCLK_USB0_APP_125>;
623 stgcrg: clock-controller@10230000 { label
624 compatible = "starfive,jh7110-stgcrg";
935 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
936 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
939 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
949 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
951 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
962 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
963 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
965 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
1066 clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
1067 <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
1069 resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
1070 <&stgcrg JH7110_STGRST_DMA1P_AHB>;
1246 <&stgcrg JH7110_STGCLK_PCIE0_TL>,
1247 <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
1248 <&stgcrg JH7110_STGCLK_PCIE0_APB>;
1250 resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
1251 <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
1252 <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
1253 <&stgcrg JH7110_STGRST_PCIE0_BRG>,
1254 <&stgcrg JH7110_STGRST_PCIE0_CORE>,
1255 <&stgcrg JH7110_STGRST_PCIE0_APB>;
1289 <&stgcrg JH7110_STGCLK_PCIE1_TL>,
1290 <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
1291 <&stgcrg JH7110_STGCLK_PCIE1_APB>;
1293 resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
1294 <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1295 <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1296 <&stgcrg JH7110_STGRST_PCIE1_BRG>,
1297 <&stgcrg JH7110_STGRST_PCIE1_CORE>,
1298 <&stgcrg JH7110_STGRST_PCIE1_APB>;