dts/starfive/jh7110-pine64-star64.dts

1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 	starfive,tx-use-rgmii-clk;
19 	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 	phy-handle = <&phy1>;
25 	phy-mode = "rgmii-id";
26 	starfive,tx-use-rgmii-clk;
27 	assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
28 	assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
32 		#address-cells = <1>;
33 		#size-cells = <0>;
34 		compatible = "snps,dwmac-mdio";
36 		phy1: ethernet-phy@1 {
47 	rx-internal-delay-ps = <1500>;
48 	motorcomm,rx-clk-drv-microamp = <2910>;
49 	motorcomm,rx-data-drv-microamp = <2910>;
50 	motorcomm,tx-clk-adj-enabled;
51 	motorcomm,tx-clk-10-inverted;
52 	motorcomm,tx-clk-100-inverted;
53 	motorcomm,tx-clk-1000-inverted;
57 	rx-internal-delay-ps = <0>;
58 	tx-internal-delay-ps = <300>;
59 	motorcomm,rx-clk-drv-microamp = <2910>;
60 	motorcomm,rx-data-drv-microamp = <2910>;
61 	motorcomm,tx-clk-adj-enabled;
62 	motorcomm,tx-clk-10-inverted;
63 	motorcomm,tx-clk-100-inverted;