dts/starfive/jh7100.dtsi

1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 	#address-cells = <2>;
14 	#size-cells = <2>;
17 		#address-cells = <1>;
18 		#size-cells = <0>;
21 			compatible = "sifive,u74-mc", "riscv";
23 			d-cache-block-size = <64>;
24 			d-cache-sets = <64>;
25 			d-cache-size = <32768>;
26 			d-tlb-sets = <1>;
27 			d-tlb-size = <32>;
29 			i-cache-block-size = <64>;
30 			i-cache-sets = <64>;
31 			i-cache-size = <32768>;
32 			i-tlb-sets = <1>;
33 			i-tlb-size = <32>;
34 			mmu-type = "riscv,sv39";
35 			next-level-cache = <&ccache>;
37 			riscv,isa-base = "rv64i";
38 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
40 			tlb-split;
42 			cpu0_intc: interrupt-controller {
43 				compatible = "riscv,cpu-intc";
44 				interrupt-controller;
45 				#interrupt-cells = <1>;
50 			compatible = "sifive,u74-mc", "riscv";
52 			d-cache-block-size = <64>;
53 			d-cache-sets = <64>;
54 			d-cache-size = <32768>;
55 			d-tlb-sets = <1>;
56 			d-tlb-size = <32>;
58 			i-cache-block-size = <64>;
59 			i-cache-sets = <64>;
60 			i-cache-size = <32768>;
61 			i-tlb-sets = <1>;
62 			i-tlb-size = <32>;
63 			mmu-type = "riscv,sv39";
64 			next-level-cache = <&ccache>;
66 			riscv,isa-base = "rv64i";
67 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
69 			tlb-split;
71 			cpu1_intc: interrupt-controller {
72 				compatible = "riscv,cpu-intc";
73 				interrupt-controller;
74 				#interrupt-cells = <1>;
78 		cpu-map {
91 	thermal-zones {
92 		cpu-thermal {
93 			polling-delay-passive = <250>;
94 			polling-delay = <15000>;
96 			thermal-sensors = <&sfctemp>;
99 				cpu-alert0 {
106 				cpu-crit {
116 	osc_sys: osc-sys {
117 		compatible = "fixed-clock";
118 		#clock-cells = <0>;
119 		clock-output-names = "osc_sys";
121 		clock-frequency = <0>;
124 	osc_aud: osc-aud {
125 		compatible = "fixed-clock";
126 		#clock-cells = <0>;
127 		clock-output-names = "osc_aud";
129 		clock-frequency = <0>;
132 	gmac_rmii_ref: gmac-rmii-ref {
133 		compatible = "fixed-clock";
134 		#clock-cells = <0>;
135 		clock-output-names = "gmac_rmii_ref";
137 		clock-frequency = <0>;
140 	gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
141 		compatible = "fixed-clock";
142 		#clock-cells = <0>;
143 		clock-output-names = "gmac_gr_mii_rxclk";
145 		clock-frequency = <0>;
149 		compatible = "simple-bus";
150 		interrupt-parent = <&plic>;
151 		#address-cells = <2>;
152 		#size-cells = <2>;
153 		dma-noncoherent;
157 			compatible = "starfive,jh7100-clint", "sifive,clint0";
159 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
163 		ccache: cache-controller@2010000 {
164 			compatible = "starfive,jh7100-ccache", "sifive,ccache0", "cache";
167 			cache-block-size = <64>;
168 			cache-level = <2>;
169 			cache-sets = <2048>;
170 			cache-size = <2097152>;
171 			cache-unified;
174 		plic: interrupt-controller@c000000 {
175 			compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
177 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
179 			interrupt-controller;
180 			#address-cells = <0>;
181 			#interrupt-cells = <1>;
186 			compatible = "snps,dw-mshc";
190 			clock-names = "biu", "ciu";
192 			data-addr = <0>;
193 			fifo-depth = <32>;
194 			fifo-watermark-aligned;
199 			compatible = "snps,dw-mshc";
203 			clock-names = "biu", "ciu";
205 			data-addr = <0>;
206 			fifo-depth = <32>;
207 			fifo-watermark-aligned;
212 			compatible = "starfive,jh7100-dwmac", "snps,dwmac";
219 			clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "gtx";
221 			reset-names = "ahb";
223 			interrupt-names = "macirq", "eth_wake_irq";
224 			max-frame-size = <9000>;
225 			snps,multicast-filter-bins = <32>;
226 			snps,perfect-filter-entries = <128>;
228 			rx-fifo-depth = <32768>;
229 			tx-fifo-depth = <16384>;
230 			snps,axi-config = <&stmmac_axi_setup>;
231 			snps,fixed-burst;
235 			stmmac_axi_setup: stmmac-axi-config {
242 		clkgen: clock-controller@11800000 {
243 			compatible = "starfive,jh7100-clkgen";
246 			clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
247 			#clock-cells = <1>;
250 		rstgen: reset-controller@11840000 {
251 			compatible = "starfive,jh7100-reset";
253 			#reset-cells = <1>;
257 			compatible = "starfive,jh7100-sysmain", "syscon";
262 			compatible = "snps,designware-i2c";
266 			clock-names = "ref", "pclk";
269 			#address-cells = <1>;
270 			#size-cells = <0>;
275 			compatible = "snps,designware-i2c";
279 			clock-names = "ref", "pclk";
282 			#address-cells = <1>;
283 			#size-cells = <0>;
288 			compatible = "starfive,jh7100-pinctrl";
291 			reg-names = "gpio", "padctl";
295 			gpio-controller;
296 			#gpio-cells = <2>;
297 			interrupt-controller;
298 			#interrupt-cells = <2>;
302 			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
306 			clock-names = "baudclk", "apb_pclk";
309 			reg-io-width = <4>;
310 			reg-shift = <2>;
315 			compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
319 			clock-names = "baudclk", "apb_pclk";
322 			reg-io-width = <4>;
323 			reg-shift = <2>;
328 			compatible = "snps,designware-i2c";
332 			clock-names = "ref", "pclk";
335 			#address-cells = <1>;
336 			#size-cells = <0>;
341 			compatible = "snps,designware-i2c";
345 			clock-names = "ref", "pclk";
348 			#address-cells = <1>;
349 			#size-cells = <0>;
354 			compatible = "starfive,jh7100-wdt";
358 			clock-names = "apb", "core";
364 			compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
368 			#pwm-cells = <3>;
372 		sfctemp: temperature-sensor@124a0000 {
373 			compatible = "starfive,jh7100-temp";
377 			clock-names = "sense", "bus";
380 			reset-names = "sense", "bus";
381 			#thermal-sensor-cells = <0>;